Implementation of a monolithic capacitive accelerometer in a wafer-level 0.18 μm CMOS MEMS process

Journal of Micromechanics and Microengineering

Volumn 22, Issue 5, 2012, Pages

  Tseng, Sheng Hsiang ^a   Lu, Michael S C ^a   Wu, Po Chang ^b   Teng, Yu Chen ^b   Tsai, Hann Huei ^b   Juang, Ying Zong ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b NATIONAL APPLIED RESEARCH LABORATORIES   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE SENSITIVITIES; CAPACITIVE ACCELEROMETERS; CHIP AREAS; CMOS-MEMS; COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; CROSS-AXIS SENSITIVITY; MASKING LAYERS; MICRO-STRUCTURAL; MICROMECHANICAL STRUCTURES; MULTI-PROJECT WAFER; NOISE FLOOR; NON-LINEARITY; OFFSET VOLTAGE; OUT-OF-PLANE; OUT-OF-PLANE DEFLECTION; SENSING CIRCUITS; SENSING RANGES; STANDARD CMOS PROCESS; STANDARD DEVIATION; SWITCHED CAPACITOR; TEMPERATURE COEFFICIENT; THICK PHOTORESISTS; TOTAL POWER CONSUMPTION; VERTICAL STRESS; WAFER LEVEL;

CMOS INTEGRATED CIRCUITS; ELECTROMECHANICAL DEVICES; PHOTORESISTS;

ACCELEROMETERS;

EID: 84860551897     PISSN: 09601317     EISSN: 13616439     Source Type: Journal    
DOI: 10.1088/0960-1317/22/5/055010     Document Type: Article

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