Comprehensive and accurate parasitic capacitance models for two- and three-dimensional CMOS device structures

IEEE Transactions on Electron Devices

Volumn 59, Issue 5, 2012, Pages 1332-1344

  Lacord, Joris ^a,b   Ghibaudo, Gérard ^b   Boeuf, Frédéric ^a  

^a STMICROELECTRONICS   (France)

^b MINATEC   (France)

Author keywords

Analytical model; benchmarking; CMOS; parasitic capacitance

Indexed keywords

BI-LAYER; CMOS; CMOS DEVICES; FLEXPDE; PARASITIC CAPACITANCE; PLANAR DOUBLE GATES; RAISED-SOURCE DRAINS; TRIPLE-GATE;

ANALYTICAL MODELS; BENCHMARKING; CAPACITANCE; CMOS INTEGRATED CIRCUITS; THREE DIMENSIONAL COMPUTER GRAPHICS;

THREE DIMENSIONAL;

EID: 84860256442     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2012.2187454     Document Type: Article

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