Impact of fringe capacitance on the performance of nanoscale finFETs

IEEE Electron Device Letters

Volumn 31, Issue 1, 2010, Pages 83-85

  Manoj, C R ^a   Sachid, Angada B ^a   Yuan, Feng ^b   Chang, Chang Yun ^b   Rao, V Ramgopal ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Epi thickness; Fin pitch; FinFETs; Fringe capacitance; Junction capacitance

Indexed keywords

CLOSE PROXIMITY; DEVICE OPTIMIZATION; FAN-OUT; FIN PITCH; FINFETS; FRINGE CAPACITANCE; JUNCTION CAPACITANCES; METAL GATE; MIXED MODE SIMULATION; MOSFETS; NANO SCALE; PARASITIC COMPONENTS; SELECTIVE EPI GROWTHS; SERIES RESISTANCES;

FINS (HEAT EXCHANGE); NANOTECHNOLOGY; THREE DIMENSIONAL;

CAPACITANCE;

EID: 72949122796     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2035934     Document Type: Article

References (10)

1. D. Hisamoto, W.-C. Lee, J. Kedzierski, J. Bokor, and C. Hu, "FinFET-A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol.47, no.12, pp. 2320-2325, Dec. 2000.
2. T.-S. Park, S. Choi, D.-H. Lee, U-I. Chung, J. T. Moon, E. Yoon, and J.-H. Lee, "Body-tied triple-gate NMOSFET fabrication using bulk Si wafer," Solid State Electron., vol.49, no.3, pp. 377-383, Mar. 2005.
3. N. Collaert, A. Dixit, M. Goodwin, K. G. Anil, R. Rooyackers, B. Degroote, L. H. A. Leunissen, A. Veloso, R. Jonckheere, K. De Meyer, M. Jurczak, and S. Biesemans, "A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node," IEEE Electron Device Lett., vol.25, no.8, pp. 568-570, Aug. 2004.
4. A. Dixit, A. Kottantharayil, N. Collaert, and K. De Meyer, "Analysis of the parasitic S/D resistance in multiple-gate FETs," IEEE Trans. Electron Devices, vol.52, no.6, pp. 1132-1140, Jun. 2005.
5. A. Kranti and G. A. Armstrong, "Performance assessment of nanoscale double-and triple-gate FinFETs," Semicond. Sci. Technol., vol.21, no.4, pp. 409-421, Apr. 2006.
6. User Manual, Sentaurus Tool Suite, Synopsys Inc., Mountain View, CA, 2008.
7. C. R. Manoj and V. R. Rao, "Impact of high-κ gate dielectrics on the device and circuit performance of nanoscale FinFETs," IEEE Electron Device Lett., vol.28, no.4, pp. 295-297, Apr. 2007.
8. A. B. Sachid, R. Francis, M. S. Baghini, D. K. Sharma, K.-H. Bach, R. Mahnkopf, and V. R. Rao, "Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?" in IEDM Tech. Dig., San Francisco, CA, Dec. 15-17, 2008, pp. 697-700.
9. R. Granzner, V. M. Polyakov, F. Schwierz, M. Kittler, R. J. Luyken, W. Rosner, and M. Stadele, "Simulation of nanoscale MOSFETs using modified drift-diffusion and hydrodynamic models and comparison with Monte Carlo results," Microelectron. Eng., vol.83, no.2, pp. 241-246, Feb. 2006.
10. C. R. Manoj, M. Nagpal, D. Varghese, and V. R. Rao, "Device design and optimization of nanoscale bulk FinFETs," IEEE Trans. Electron Devices, vol.55, no.2, pp. 609-615, Feb. 2008.