A solution for an ideal planar multi-gates process for ultimate CMOS?

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2010, Pages

  Monfray, S ^a,b   Huguenin, J L ^a,c   Martin, M ^b   Samson, M P ^a,b   Borowiak, C ^a   Arvet, C ^a,b   Dalemcourt, J F ^b   Perreau, P ^a,b   Barnola, S ^b   Bidal, G ^a   Denorme, S ^a   Campidelli, Y ^a   Benotmane, K ^b   Leverd, F ^a   Gouraud, P ^a   Le Gratiet, B ^a   De Buttet, C ^a,b   Pinzelli, L ^a   Beneyton, R ^a   Morel, T ^a   Wacquez, J ^b   Bustos, ^a   Icard, B ^b   Pain, L ^b   Barraud, S ^b   Ernst, T ^b   Boeuf, F ^a   Faynot, O ^b   Skotnicki, T ^a   more..

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

^c IMEP LAHC   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CONDUCTION CHANNEL; DRIVE CURRENTS; GATE PROCESS; MULTI-GATES; SELF-ALIGNED;

ELECTRON DEVICES;

EID: 79951826368     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703339     Document Type: Conference Paper

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8. Wong et al., VLSI 2009
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11. Huguenin et al, tbp at SSDM 2010
12. M.Lenzi et al, IEEE TED, vol55, No 8, 2008
13. S.Monfray et al, IEDM 2007
14. R.Wacquez et al, SSDM 2007.