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J.Mitard, B. De Jaeger, F.E. Leys, G. Hellings, G.; Martens, K. ; Eneman, G.; Brunco, D.P.; Loo, R.; Lin, J.C.; Shamiryan, D.; Vandeweyer, T.; Winderickx, G.; Vrancken, E.; Yu, C.H.; De Meyer, K.; Caymax, M.; Pantisano, L.; Meuris, M.; Heyns, "Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability", International Electron Devices Meeting (IEDM), 2008.
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77957861097
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8Å Tinv Gate-First Dual Channel Technology Achieving Low-Vt High Performance CMOS
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L. Witters, S. Takeoka, S. Yamaguchi, A.Hikavyy, D. Shamiryan, M.J. Cho, T. Chiarella, L.-Å. Ragnarsson, R.Loo, C. Kerner, Y. Crabbe, J. Franco, J. Tseng, W.-E. Wang, E. Rohr, T. Schram, O. Richard, H. Bender, S. Biesemans, P. Absil, T.Hoffmann, "8Å Tinv Gate-First Dual Channel Technology Achieving Low-Vt High Performance CMOS", VLSI Symposium Tech. Dig., 2010.
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74349115688
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A.Hikavyy, R.Loo, L.Witters S. Takeoka, J. Geypen, B.Brijs, C. Merckling, M.Caymax and J. Dekoster, "SiGe SEG Growth For Buried Channel p-MOS Devices", ECS Transactions, 25 (7),p.201-210, 2009.
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E. Rosseel, A. Hikavyya, J-L Everaert, L. Witters, J. Mitard, T. Hoffmann, W. Vandervorst, A. Pap and T. Pavelka, "Impact of laser anneal thermal budget on the quality of thin SiGe channels with a high Ge content", submitted to 18th IEEE International Conference on Advanced Thermal Processing of Semiconductors - RTP 2010.
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46049083423
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High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates
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Tateshita, Y.; Wang, J.; Nagano, K.; Hirano, T.; Miyanami, Y.; Ikuta, T.; Kataoka, T.; Kikuchi, Y.; Yamaguchi, S.; Ando, T.; Tai, K.; Matsumoto, R.; Fujita, S.; Yamane, C.; Yamamoto, R.; Kanda, S.; Kugimiya, K.; Kimura, T.; Ohchi, T.; Yamamoto, Y.; Nagahama, Y.; Hagimoto, Y.; Wakabayashi, H.; Tagawa, Y.; Tsukamoto, M.; Iwamoto, H.; Saito, M.; Kadomura, S.; Nagashima, N.; "High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates", International Electron Devices Meeting (IEDM), 2008.
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Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements
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DOI: 10.1109/TVLSI.2010.2053226
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P. Magnone, F. Crupi, M. Alioto, B. Kaczer, B. De Jaeger, "Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits from Experimental Measurements", IEEE Transactions on VLSI Systems, DOI: 10.1109/TVLSI.2010.2053226.
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The Effective Drive Current in CMOS Inverters
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M.H. Na, E. J. Nowak, W. Haensch, J. Cai, "The Effective Drive Current in CMOS Inverters", International Electron Devices Meeting (IEDM), 2002.
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12
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77952371631
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Advanced High-K Gate Dielectric for High-Performance Short-Channel In0.7Ga0.3As Quantum Well Field Effect Transistors on Silicon Substrate for Low Power Logic Applications
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M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M. K. Hudait, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, W. Rachmady, U. Shah and Robert Chau, "Advanced High-K Gate Dielectric for High-Performance Short-Channel In0.7Ga0.3As Quantum Well Field Effect Transistors on Silicon Substrate for Low Power Logic Applications", International Electron Devices Meeting (IEDM), 2009.
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