Fast and accurate analytical modeling of through-silicon-via capacitive coupling

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 1, Issue 2, 2011, Pages 168-180

  Kim, Dae Hyun ^a   Mukhopadhyay, S ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Capacitance; three dimensional integrated circuits (3D IC); through silicon via (TSV); timing analysis

Indexed keywords

CAPACITANCE ESTIMATION; CAPACITIVE COUPLINGS; COUPLING CAPACITANCE; FAST CAPACITANCE; THREE DIMENSIONAL INTEGRATED CIRCUITS; THROUGH SILICON VIAS; THROUGH-SILICON VIA; TIMING ANALYSIS;

ANALYTICAL MODELS; CAPACITANCE; COMPUTER AIDED DESIGN; ELECTRONICS PACKAGING; ESTIMATION; INTEGRATED CIRCUITS; RANDOM ERRORS; THREE DIMENSIONAL COMPUTER GRAPHICS;

THREE DIMENSIONAL;

EID: 84859030874     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2010.2101910     Document Type: Article

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