Timing-driven via placement heuristics for three-dimensional ICs

Integration, the VLSI Journal

Volumn 41, Issue 4, 2008, Pages 489-508

  Pavlidis, Vasilis F ^a   Friedman, Eby G ^a  

^a University of Rochester   (United States)

Author keywords

3 D ICs; Design aids; Elmore delay; Interconnect optimization; Interplane interconnects; Interplane vias; Placement; RC interconnects; Three dimensional integration; Through silicon vias; Timing optimization; TSV placement

Indexed keywords

DESIGN AIDS; HEURISTIC ALGORITHMS; INTERCONNECTION NETWORKS; NETWORK ROUTING; OPTIMIZATION; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE;

ELMORE DELAY; INTERCONNECT OPTIMIZATION; INTERPLANE INTERCONNECTS; INTERPLANE VIAS; THREE DIMENSIONAL INTEGRATION; THROUGH SILICON VIAS; TIMING OPTIMIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 43949128770     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2007.11.002     Document Type: Article

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