3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Katti, G ^a,b   Mercha, A ^a   Van Olmen, J ^a   Huyghebaert, C ^a   Jourdain, A ^a   Stucchi, M ^a   Rakowski, M ^a   Debusschere, I ^a   Soussan, P ^a   Dehaene, W ^a   De Meyer, K ^a   Travaly, Y ^a   Beyne, E ^a   Biesemans, S ^a   Swinnen, B ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

3D CIRCUIT; COST-EFFECTIVE SOLUTIONS; D-RINGS; HYBRID BONDING; POWER DELAYS; PROCESS ROUTE; THROUGH SILICON VIAS;

DIES; ELECTRON DEVICES; OSCILLATORS (ELECTRONIC); SILICON WAFERS; THREE DIMENSIONAL;

WAFER BONDING;

EID: 77952350733     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424351     Document Type: Conference Paper

References (4)

1. E. Beyne, "System-Driven Approaches to 3D Integration", Proceedings 4th International Symposium on Microelectronics and Packaging, Seoul, South Korea,Sep. 28, 2005.
2. B. Swinnen et al., "3D integration by Cu-Cu thermocompression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias", Technical Digest of the International Electron Device Meeting 2006, pp. 371-374.
3. Jan Van Olmen et al., "3D Stacked IC Demonstration using a Trough Silicon Via First Approach", Technical Digest of the International Electron Device Meeting 2008, pp. 603-616.
4. Anne Jourdain et al., "Electrically Yielding Collective Hybrid Bonding for 3D Stacking of ICs", Electronic Components and Technology Conference 2009, pp. 11 - 13.