Zero-sleep-leakage flip-flop circuit with conditional-storing memristor retention latch

IEEE Transactions on Nanotechnology

Volumn 11, Issue 2, 2012, Pages 360-366

  Jung, Chul Moon ^a   Jo, Kwan Hee ^b   Lee, Eun Sub ^a   Vo, Huan Minh ^a   Min, Kyeong Sik ^a  

^a Kookmin University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

Conditional storing technique; memristor retention latch; power gating scheme; zero sleep leakage flip flop

Indexed keywords

CONDITIONAL-STORING TECHNIQUE; EXTERNAL POWER SUPPLIES; MEMRISTOR; POWER GATING SCHEME; SLEEP TIME; SWITCHING POWER; ZERO-SLEEP-LEAKAGE FLIP-FLOP;

MEMRISTORS; PASSIVE FILTERS; RESISTORS; SLEEP RESEARCH;

FLIP FLOP CIRCUITS;

EID: 84858375750     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2011.2175943     Document Type: Article

References (21)

1. D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The missing memristor found," Nature, vol. 453, pp. 80-83, 2008.
2. L. A. Agapito, S. Alkis, J. L. Krause, and H.-P. Cheng, "Atomistic origins of molecular memristors," J. Phys. Chem. C, vol. 113, no. 48, pp. 20713- 20718, Nov. 2009.
3. 2 /Ag interfaces and their role in memristor devices," Phys. Rev. B, vol. 83, pp. 245314-1-245314-9, Jun. 2011.
4. G. S. Snider, "Spike-timing-dependent learning in memristive nanodevices," in Proc. IEEE Int. Symp. Nanoscale Archit., 2008, pp. 85-92.
5. C. J. Chevallier, C. H. Siau, S. F. Lim, S. R. Namala, M. Matsuoka, B. L. Bateman, and D. Rinerson, "A 0.13 μm64Mbmulti-layered conductive metal-oxide memory," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2010, pp. 260-261.
6. K.-H. Jo, E.-S. Lee, and K.-S. Min, "Zero-standby-power flip-flop circuit using memristive devices," presented at the Int. Conf. Electron. Mater. Int. Union Mater. Res. Soc., Seoul, Korea, Aug. 2010.
7. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
8. S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, "A 1-V high-speed MTCMOS circuit scheme for power-down application circuits," IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 861-869, Jun. 1997.
9. T. Shirai and K. Usami, "Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations," in Proc. Int. SoC Design Conf., Nov. 2008, pp. I-310-I-313.
10. Y. Takeyama, H. Otake, O. Hirabayashi, K. Kushida, and N. Otsuka, "A low leakage SRAM macro with replica cell biasing scheme," in Proc. Symp. VLSI Circuits, Jul., 2005, pp. 166-167.
11. R. Vullers, R. Schajk, H. Visser, J. Penders, and C. Hoof, "Energy harvesting for autonomous wireless sensor networks," IEEE Solid-State Circuits Mag., vol. 2, no. 2, pp. 29-38, Spring 2010.
12. J. H. Bong, K. H. Jo, K. S.Min, and S. M. Kang, "Oxide-tunneling leakage suppressed SRAMfor sub-65-nm VLSI's," J. Low Power Electron., vol. 7, no. 1, pp. 87-95, Feb. 2011.
13. Y. R. Wang and Z. G. Yu, "A high-efficiency cross-coupled charge pump for flash memories," in Proc. Int. Conf. Adv. Comput. Control, Jun. 2010, vol. 3, pp. 130-133.
14. S. E. Ahn, M. J. Lee, Y. Park, B. S. Kang, C. B. Lee, K. H. Kim, S. Seo, D. S. Suh, D. C. Kim, J. Hur, W. Xianyu, G. Stefanovich, H. Yin, I. K. Yoo, J. H. Lee, J. B. Park, I. G. Baek, and B. H. Park, "Write current reduction in transition metal oxide based resistance-change memory," Adv. Mater., vol. 20, pp. 924-928, Feb. 2008.
15. C. Cagli, F. Nardi, and D. Ielmini, "Modeling of set/reset operation in NiO-based resistive-switching memory devices," IEEE Trans. Electron Devices, vol. 56, no. 8, pp. 1712-1720, Aug. 2009.
16. K. S. Min, H. D. Choi, H. Y. Choi, H. Kawaguchi, and T. Sakurai, "Leakage-suppressed clock-gating circuit with zigzag super cut-off CMOS (ZSSCCMOS) for leakage-dominant sub-70-nm and sub-1-VVDD LSIs," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 4, pp. 430-435, Apr. 2006.
17. K.-H. Jo, C.-M. Jung, K.-S. Min, and S.-M. Kang, "Self-adaptive write circuit for low-power and variation-tolerant memristors," IEEE Trans. Nanotechnol., vol. 9, no. 6, pp. 675-678, Nov. 2010.
18. Predictive Technology Model (PTM) (2008). [Online]. Available: http:// ptm.asu.edu
19. S. H. Jo, K. H. Kim, T. Chang, S. Gaba, andW. Lu, "Si memristive devices applied to memory and neuromorphic circuits," in Proc. IEEE Int. Symp. Circuits Syst., May/Jun. 2010, pp. 13-16.
20. W. Lu,K.H.Kim, T.Chang, and S.Gaba, "Two-terminal resistive switches (memristors) formemory and logic applications," in Proc. 16th Asia South Pacific Design Autom. Conf., Jan. 2011, pp. 217-223.
21. International technology road-map for semiconductors. (2009). [Online]. Available: http://www.itrs.net