Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

2008 International SoC Design Conference, ISOCC 2008

Volumn 1, Issue , 2008, Pages

  Shirai, Toshiaki ^a   Usami, Kimiyoshi ^a  

^a SHIBAURA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Dual Vth; Leakage current; Low power; MTCMOS; Power gating; Vth variation

Indexed keywords

DUAL VTH; LOW POWER; MTCMOS; POWER GATING; VTH VARIATION;

CELL MEMBRANES; CMOS INTEGRATED CIRCUITS; DESIGN; PROGRAMMABLE LOGIC CONTROLLERS; SIMULATED ANNEALING; TIME DELAY;

LEAKAGE CURRENTS;

EID: 69949089010     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCDC.2008.4815634     Document Type: Conference Paper

References (11)

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