Demystifying surrogate modeling for circuits and systems

IEEE Circuits and Systems Magazine

Volumn 12, Issue 1, 2012, Pages 45-63

  Yelten, Mustafa Berke ^a   Zhu, Ting ^b   Koziel, Slawomir ^c   Franzon, Paul D ^b   Steer, Michael B ^b  

^a INTEL CORPORATION   (United States)

^b North Carolina State University   (United States)

^c REYKJAVIK UNIVERSITY   (Iceland)

Author keywords

[No Author keywords available]

Indexed keywords

BLACK-BOX MODELING; CHEMICAL PROCESS; COMPLEX STRUCTURE; DESIGN TOOL; ELECTROMAGNETIC MODELING; GREY-BOX; MACROMODELING; MATHEMATICAL FOUNDATIONS; PHYSICAL WORLD; SURROGATE MODEL; SURROGATE MODELING;

AIRFOILS;

FUEL ADDITIVES;

EID: 84858270643     PISSN: 1531636X     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCAS.2011.2181095     Document Type: Article

References (73)

1. I. G. Osio and C. H. Amon, "An engineering design methodology with multistage Bayesian surrogates and optimal sampling," Res. Eng. Des., vol. 8, no. 4, pp. 189-206, Dec. 1996. (Pubitemid 126610228)
2. J. W. Bandler, R. M. Biernacki, S. H. Chen, P. A. Grobelny, and R. H. Hemmers, "Space mapping technique for electromagnetic optimization," IEEE Trans. Microwave Theory Tech., vol. 42, no. 12, pp. 2536-2544, Dec. 1994.
3. R. Pally, "The predicting brain: Unconscious repetition, conscious refl ection and therapeutic change," Int. J. Psychoanal., vol. 88, no. 4, pp. 861-881, Aug. 2007. (Pubitemid 47278211)
4. J. Hawkins and S. Blakeslee, On Intelligence. New York: Macmillan, 2005.
5. M. B. Yelten, P. D. Franzon, and M. B. Steer, "Surrogate model-based analysis of analog circuits-Part I: Variability analysis," IEEE Trans. Device Mater. Rel., vol. 11, no. 3, pp. 458-465, Sept. 2011.
6. J. W. Bandler, Q. S. Cheng, S. A. Dakroury, A. S. Mohamed, M. H. Bakr, K. Madsen, and J. Søndergaard, "Space mapping: The state of the art," IEEE Trans. Microwave Theory Tech., vol. 52, no. 1, pp. 337-361, Jan. 2004.
7. T. C. Edwar ds and M. B. Steer, Foundations of Interconnect and Microstrip Design. West Sussex, U.K.: Wiley, 2000.
8. P. Li and L . T. Pileggi, "Compact reduced-order modeling of weakly nonlinear analog and RF circuits," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 23, no. 2, pp. 184-203, Feb. 2005. (Pubitemid 40178518)
9. A. A. Giunt a, S. F. Wojtkiewicz, and M. S. Eldred, "Overview of modern design of experiments methods for computational simulations," in Proc. 41st Aerospace Sciences Meeting and Exhibit, Reno, NV, Jan. 2003, pp. 1-17.
10. A. Forreste r, A. Sobester, and A. Keane, Engineering Design via Surrogate Modelling. West Sussex, U.K.: Wiley, 2008.
11. Z. N. Mevaw alla, G. S. May, and M. W. Kiehlbauch, "Neural network modeling for advanced process control using production data," IEEE Trans. Semicond. Manuf., vol. 24, no. 2, pp. 182-189, May 2011.
12. T. Kiely and G. Gielen, "Performance modeling of analog integrated circuits using least-squares support vector machines," in Proc. Design, Automation and Test in Europe Conf. Exhibition, DATE, Paris, France, Feb. 2004, pp. 448-453.
13. S. Haykin, Neural Networks and Learning Machines, 3rd ed. New Jersey: Pearson, 2009.
14. S. Koziel a nd J. Bandler, "Recent advances in space-mapping-based modeling of microwave devices," Int. J. Numer. Model. Electron. Netw. Devices Fields, vol. 23, no. 6, pp. 425-446, Nov. 2010.
15. A. J. Keane and P. B. Nair, Computational Approaches for Aerospace Design. West Sussex, U.K.: Wiley, 2005.
16. M. Small and C. K. Tse, "Detecting determinism in time series: The method of surrogate data," IEEE Trans. Circuits Syst. I, vol. 50, no. 5, pp. 663-672, May 2003.
17. M. D. Morri s, "Factorial sampling plans for preliminary computational experiments," Technometrics, vol. 33, no. 2, pp. 161-174, May 1991.
18. D. Child, T he Essentials of Factor Analysis. New York: Continuum International Publishing, 2006.
19. A. Mitev, M . Marefat, D. Ma, and J. M. Wang, "Principle Hessian direction-based parameter reduction for interconnect networks with process variation," IEEE Trans. VLSI Syst., vol. 18, no. 9, pp. 1337-1347, Sept. 2010.
20. Z. Feng and P. Li, "Performance-oriented parameter dimension reduction of VLSI circuits," IEEE Trans. VLSI Syst., vol. 17, no. 1, pp. 137-150, Jan. 2009.
21. Z. Li, X. L u, and W. Shi, "Process variation dimension reduction based on SVD," in Proc. IEEE Int. Symp. Circuits and Systems, ISCAS, Bangkok, Thailand, May 2003, pp. IV(672)-IV(675
22. X. Li, J. L e, L. T. Pileggi, and A. Strojwas, "Projection-based performance modeling for inter/intra-die variations," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, ICCAD, San Jose, CA, Nov. 2005, pp. 721-727.
23. A. Mitev, M . Marefat, D. Ma, and J. M. Wang, "Parameter reduction for variability analysis by slice inversion regression method," IET Circuits, Devices Syst., vol. 2, no. 1, pp. 16-22, Feb. 2008. (Pubitemid 351342383)
24. M. D. McKay , R. J. Beckman, and W. J. Conover, "A comparison of three methods for selecting values of input variables in the analysis of output from a computer code," Technometrics, vol. 21, no. 2, pp. 239-245, May 1979. (Pubitemid 9452235)
25. B. Tang, "O rthogonal array-based latin hypercubes," J. Amer. Statist. Assoc., vol. 88, no. 424, pp. 1392-1397, Dec. 1993.
26. M. B. Yelte n, P. D. Franzon, and M. B. Steer, "Comparison of modeling techniques for circuit variability analysis," Int. J.Numerical Modelling: Electron. Netw., Devices Fields, to be published.
27. T.-T. Wong, W.-S. Luk, and P.-A. Heng, "Sampling with Hammersley and Holton points," J. Graph. Tools, vol. 2, pp. 1-16, 1997.
28. D. Deschrij ver, K. Crombecq, H. Nguyen, and T. Dhaene, "Adaptive sampling algorithm for macromodeling of parameterized S-parameter responses," IEEE Trans. Microwave Theory Tech., vol. 59, no. 1, pp. 39-45, Jan. 2011.
29. K. Crombecq , L. D. Tommasi, D. Gorissen, and T. Dhaene, "A novel sequential design strategy for global surrogate modeling," in Proc. Winter Simulation Conference WSC, Austin, TX, Dec. 2009, pp. 731-742.
30. D. Gorissen , K. Crombecq, I. Couckuyt, T. Dhaene, and P. Demeester, "A surrogate modeling and adaptive sampling toolbox for computer-based design," J. Machine Learn. Res., vol. 11, no. 5, pp. 2051-2055, July 2010.
31. J. E. Ráyas-Sanchez, J. Aguliar-Torrentera, and J. A. Jasso-Urzúa, "Surrogate modeling of microwave circuits using polynomial function interpolants," in Proc. IEEE Int. Microwave Symp., IMS, Anaheim, CA, May 2010, pp. 197-200.
32. H. Filiol, I. O'Conno r, and D. Morche, "A new approach for variability analysis of ICs," in Proc. IEEE European Conf. Circuit Theory and Design, ECCTD, Antalya, Turkey, Aug. 2009, pp. 237-240.
33. J. P. C. Kleijnen, "K riging metamodeling in simulation: A review," Eur. J. Operation. Res., vol. 192, no. 3, pp. 707-716, Feb. 2009.
34. J. D. Martin, "Comput ational improvements to estimating Kriging metamodel parameters," ASME J. Mech. Des., vol. 131, no. 084501, pp. 1-7, Aug. 2009.
35. S. N. Lophaven, H. B. Nielsen, and J. Søndergaard. (2002, Aug.). A MATLAB Kriging toolbox version 2.0. [Online]. Available: Http://www2.imm.dtu. dk/~hbn/dace/dace.pdf
36. D. Gorissen, L. D. Tommasi, W. H endrickx, J. Croon, and T. Dhaene, "RF circuit block modeling via Kriging surrogates," in Proc.17th Int. Conf. Microwaves, Radar and Wireless Communications, MIKON, Wroclaw, Poland, May 2008, pp. 1-4.
37. H. You, M. Yang, D. Wang, and X. Jia, "Kriging model combined with Latin hypercube sampling for surrogate modeling of analog integrated circuit performance," in Proc. IEEE Int. Symp. Quality of Electronic Design, ISQED, San Jose, CA, Mar. 2009, pp. 554-558.
38. G. Yu and P. Li, "Yield-aware an alog integrated circuit optimization using geostatics motivated performance modeling," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, ICCAD, San Jose, CA, Nov. 2007, pp. 464-469.
39. D. Gorissen, L. D. Tommasi, K. C rombecq, and T. Dhaene, "Sequential modeling of a low noise amplifi er with neural networks and active learning," Neural Comput. Applicat., vol. 18, no. 5, pp. 485-494, June 2009.
40. B. Liu, D. Zhao, P. Reynaert, and G. Gielen, "Synthesis of integrated passive components for high-frequency RF ICs based on evolutionary computation and machine learning techniques," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 30, no. 10, pp. 184-203, Oct. 2011.
41. L. Zhang, Q.-J. Zhang, and J. Wo od, "Statistical neuro-space mapping technique for large-signal modeling of nonlinear devices," IEEE Trans. Microwave Theory Tech., vol. 56, no. 11, pp. 2453-2467, Nov. 2008.
42. A. Díaz-Manríquez, G. Toscano-Pu lido, and W. Gómez-Flores, "On the selection of surrogate models in evolutionary optimization algorithms," in Proc. IEEE Congr. Evolutionary Computation, CEC, New Orleans, LA, June 2011, pp. 2155-2162.
43. J. A. K. Suykens, T. V. Gestel, J. D. Brabanter, B . D. Moor, and J. Vandewalle, Least Squares Support Vector Machines. Singapore: World Scientific, 2002.
44. K. D. Brabanter, P. Karsmakers, F. Ojeda, C. Alzat e, J. D. Brabanter, K. Pelckmans, B. D. Moor, J. Vandewalle, and J. A. K. Suykens. (2010, Sept.). LSSVMlab toolbox version 1.7. [Online]. Available: Http://www.esat.kuleuven. be/sista/lssvmlab
45. L. Xia, J. Meng, R. Xu, B. Yan, and Y. Guo, "Model ing of 3-D vertical interconnect using support vector machine regression," IEEE Microwave Wireless Compon. Lett., vol. 16, no. 12, pp. 639-641, Dec. 2006. (Pubitemid 44925833)
46. G. Angiulli, M. Cacciola, and M. Versaci, "Microwa ve devices and antennas modelling by support vector regression machines," IEEE Trans. Magn., vol. 43, no. 4, pp. 1589-1592, Apr. 2007. (Pubitemid 46495538)
47. S. Koziel, J. W. Bandler, and K. Madsen, "A space mapping framework for engineering optimization: Theory and implementation," IEEE Trans. Microwave Theory Tech., vol. 54, no. 10, pp. 3721-3730, Oct. 2006. (Pubitemid 44559581)
48. N. V. Queipo, R. T. Haftka, W. Shyy, T. Goel, R. V aidyanathan, and P. K. Tucker, "Surrogate-based analysis optimization," Progr. Aerospace Sci., vol. 41, pp. 1-28, Jan. 2005.
49. N. M. Alexandrov, J. E. Dennis, R. M. Lewis, and V . Torczon, "A trust region framework for managing use of of approximation models in optimization," Struct. Multidiscip. Optim., vol. 15, no. 1, pp. 16-23, Feb. 1998. (Pubitemid 128647612)
50. H. Kabir, Y. Wang, M. Yu, and Q. J. Zhang, "Neural network inverse modeling and applications to microwave fi lter design," IEEE Trans. Microwave Theory Tech., vol. 56, no. 4, pp. 867-879, Apr. 2008. (Pubitemid 351506234)
51. Q. S. Cheng, J. C. Rautio, J. W. Bandler, and S. K oziel, "Progress in simulator-based tuning-The art of tuning space mapping," IEEE Microwave Mag., vol. 11, no. 4, pp. 96-110, June 2010.
52. "em," Sonnet Software, Inc., North Syracuse, NY, 20 10, version 12.54.
53. N. M. Alexandrov and R. M. Lewis, "An overview of fi rst-order model management for engineering optimization," Optim. Eng., vol. 2, no. 4, pp. 413-430, Dec. 2001.
54. D. Echeverria and P. W. Hemker, "Space mapping and defect correction," CMAM Int. Math. J. Computat. Methods Appl. Math., vol. 5, pp. 107-136, 2005.
55. S. Koziel, "Shape-preserving response prediction f or microwave design optimization," IEEE Trans. Microwave Theory Tech., vol. 58, no. 11, pp. 2829-2837, Nov. 2010.
56. A. I. J. Forrester and A. J. Keane, "Recent advanc es in surrogate-based optimization," Progr. Aerosci. Sci., vol. 45, no. 1-3, pp. 50-79, Jan. 2009.
57. M. H. M. Salleh, G. Prigent, O. Pigaglio, and R. C rampagne, "Quarterwavelength side-coupled ring resonator for bandpass fi lters," IEEE Trans. Microwave Theory Tech., vol. 56, no. 1, pp. 156-162, Jan. 2008.
58. "FEKO," EM Software & Systems-S.A. (Pty) Ltd., Ste llenbosch, South Africa, 2010, suite 6.0.
59. "Agilent ADS," Agilent Technologies, Santa Rosa, CA , 2008, version 2008.
60. S. Koziel, "Role of constraints in surrogate-based design optimization of microwave structures," IET Microwaves, Antennas Propagat., vol. 5, no. 5, pp. 588-595, Apr. 2011.
61. IO buffer information specifi cation (ibis). [Online ]. Available: Http:/www.eda.org/ibis
62. T. Zhu, M. B. Steer, and P. D. Franzon, "Accurate and scalable IO buffer macromodel based on surrogate modeling," IEEE Trans. Compon. Packag. Manufact. Technol., vol. 1, no. 8, pp. 1240-1249, Aug. 2011.
63. A. Muranyi. (2006, Mar.). Accuracy of IBIS models with reactive loads. [Online]. Available: Http://www.eda.org/ibis/summits/mar06/muranyi1. pdf
64. M. LaBonte and A. Muranyi. (2007, Mar.). IBIS adva nced technology modeling task group work-achievement: Verilog-a element library HSPICE test. [Online]. Available: Http://vhdl.org/pub/ibis/macromodel?wip/archive-date.html
65. J. B. Bernstein, M. Gurfi nkel, X. Li, J. Walters, Y. Shapira, and M. Talmor, "Electronic circuit reliability modeling," Microelect ron. Rel., vol. 46, pp. 1957-1979, 2006. (Pubitemid 44436279)
66. W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda, S. Krishnan, and Y. Cao, "Compact modeling and simulation of circuit reliability for 6 5-nm CMOS technology," IEEE Trans. Device Mater. Rel., vol. 7, no. 4, pp. 509-517, Dec. 2007.
67. H. Kufl uoglu and M. A. Alam, "Theory of interface-trap-induced NBTI degradation for reduced cross section MOSFETs," IEEE Trans. Electron Dev., vol. 53, no. 5, pp. 1120-1130, May 2006.
68. M. Orshansky, S. R. Nassif, and D. Boning, Design for Manufacturability and Statistical Design: A Constructive Approach. New York: Sprin ger-Verlag, 2008.
69. N. Drego, A. Chandrakasan, and D. Boning, "All-digital circuits for measurement of spatial variation in digital circuits," IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 640-651, Mar. 2010.
70. "Virtuoso analog design environment XL user guide," product version 6.1.2, Cadence Design Systems, Oct. 2007.
71. S. K. Saha, "Modeling process variability in scaled CMOS technology," IEEE Des. Test. Comput., vol. 27, no. 2, pp. 8-16, 2010.
72. M. B. Yelten, P. D. Franzon, and M. B. Steer, "Surrogate model-based analysis of analog circuits-Part II: Reliability analysis," IEEE Tr ans. Device Mater. Rel., vol. 11, no. 3, pp. 466-473, Sept. 2011.
73. T. H. Morshed, W. Yang, M. V. Dunga, X. Xi, J. He, W. Liu, K. Yu, M. Cao, X. Jin, J. J. Ou, M. Chan, A. M. Niknejad, and C. Hu. (2009, A pr.). BSIM4.6.4 MOSFET model-User's manual. [Online]. Available: Http://www-device. eecs.berkeley.edu/~bsim3/BSIM4/BSIM464/BSIM464?Manual.pdf