Performance-oriented parameter dimension reduction of VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 1, 2009, Pages 137-150

  Feng, Zhuo ^a   Li, Peng ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

Circuit simulation; Interconnect modeling; Process variation; Statistical parameter dimension reduction

Indexed keywords

CIRCUIT SIMULATION; CIRCUIT THEORY; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE;

CIRCUIT DESIGNS; CIRCUIT MODELING; CIRCUIT MODELS; CMOS DIGITAL CIRCUITS; GROWING PROCESS; INTERCONNECT MODELING; MODELING COMPLEXITY; ORDER OF MAGNITUDES; PARAMETER REDUCTIONS; PARAMETERIZED; PARAMETRIC VARIATIONS; PERFORMANCE ANALYSIS; PERFORMANCE-ORIENTED PARAMETERS; PROCESS VARIATION; REDUCED RANK REGRESSIONS; SAMPLING-BASED; SIMULATION COSTS; STATISTICAL PARAMETER DIMENSION REDUCTION; SUB CIRCUITS; VLSI SYSTEM DESIGNS; VLSI TECHNOLOGIES;

VLSI CIRCUITS;

EID: 58849152140     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2002489     Document Type: Article

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