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Volumn 4, Issue , 2003, Pages

Process variation dimension reduction based on SVD

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATION THEORY; PRINCIPAL COMPONENT ANALYSIS; TIMING CIRCUITS;

EID: 0038419536     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (15)

References (8)
  • 1
    • 0032641923 scopus 로고    scopus 로고
    • Model order reduction of RC (L) interconnect including variational analysis
    • Y. Liu, L. Pileggi and A. J. Strojwas, Model order reduction of RC (L) interconnect including variational analysis, DAC 1999, 201-206.
    • (1999) DAC , pp. 201-206
    • Liu, Y.1    Pileggi, L.2    Strojwas, A.J.3
  • 2
    • 0033699258 scopus 로고    scopus 로고
    • Impact of interconnect variations on the clock skew of a gigahertz microprocessor
    • Y. Liu, S. Nassif, L. Pileggi and A. J. Strojwas, Impact of interconnect variations on the clock skew of a gigahertz microprocessor, DAC 2000, 168-171.
    • (2000) DAC , pp. 168-171
    • Liu, Y.1    Nassif, S.2    Pileggi, L.3    Strojwas, A.J.4
  • 3
    • 84949959155 scopus 로고    scopus 로고
    • Timing and yield estimation from static timing analysis
    • A. Gattiker, S. Nassif, R. Dinakar and C. Long, Timing and yield estimation from static timing analysis, ISQED 2001, 437-442.
    • (2001) ISQED , pp. 437-442
    • Gattiker, A.1    Nassif, S.2    Dinakar, R.3    Long, C.4
  • 4
    • 0031077147 scopus 로고    scopus 로고
    • Analysis and decomposition of spatial variation in integrated circuit process and devices
    • Feb
    • B. Stine, et al., Analysis and decomposition of spatial variation in integrated circuit process and devices, IEEE Trans. Semiconductor Manufacturing, Vol. 10, No. 1, Feb 1997, 24-41.
    • (1997) IEEE Trans. Semiconductor Manufacturing , vol.10 , Issue.1 , pp. 24-41
    • Stine, B.1
  • 5
    • 0034833288 scopus 로고    scopus 로고
    • Modeling and analysis of manufacturing variations
    • S. R. Nassif, Modeling and analysis of manufacturing variations, CICC 2001.
    • (2001) CICC
    • Nassif, S.R.1
  • 7
    • 0033684002 scopus 로고    scopus 로고
    • An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects
    • C. Guardiani, S. Saxena, P. McNamara, P. Schumaker, D. Coder, An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects, DAC 2000, 15-18.
    • (2000) DAC , pp. 15-18
    • Guardiani, C.1    Saxena, S.2    McNamara, P.3    Schumaker, P.4    Coder, D.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.