Nonvolatile flash memory device using Ge nanocrystals embedded in HfAlO High-κ tunneling and control oxides: Device fabrication and electrical performance

IEEE Transactions on Electron Devices

Volumn 51, Issue 11, 2004, Pages 1840-1848

  Chen, Jing Hao ^a   Wang, Ying Qian ^a   Yoo, Won Jong ^a   Yeo, Yee Chia ^a   Samudra, Ganesh ^a   Chan, Daniel S H ^a   Du, An Yan ^b   Kwong, Dim Lee ^c  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

^c The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRON TRAPS; ELECTRON TUNNELING; EMBEDDED SYSTEMS; GIBBS FREE ENERGY; HAFNIUM COMPOUNDS; NANOSTRUCTURED MATERIALS; NONVOLATILE STORAGE; SEMICONDUCTING GERMANIUM; THERMODYNAMIC STABILITY;

FLOATING GATE (FG); NONVOLATILE FLASH MEMORY;

FLASH MEMORY;

EID: 8144221080     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.837011     Document Type: Article

References (27)

1. J. Blauwe, "Nanocrystal nonvolatile memory devices," IEEE Trans. Nanotechnol., vol. 1, pp. 72-77, Mar. 2002.
2. B. De Salvo et al., "How far will Silicon nanocrystals push the scaling limits of NVM technologies?," in IEDM Tech. Dig., 2003, pp. 597-600.
3. R. Muralidhar et al., "A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory," in IEDM Tech. Dig., 2003, pp. 601-604.
4. S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and D. Buchanan, "Volatile and nonvolatile memories in silicon with nanocrystal storage," in IEDM Tech. Dig., 1995, pp. 424-521.
5. H. I. Hanafi, S. Tiwari, and I. Khan, "Fast and long retention-time nanocrystal memory," IEEE Trans. Electron Devices, vol. 43, pp. 1553-1558, Sept. 1996.
6. [i#x," in IEDM Tech. Dig., 1998, pp. 115-118.
7. Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, "Metal nanocrystal memories - Part I: device design and fabrication," IEEE Trans. Electron Devices, vol. 49, pp. 1606-1613, Sept. 2002.
8. Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, "Effects of interface traps on charge s retention characteristics in silicon-quantum-dot-based metal-oxidesemiconductor diodes," Jpn. J. Appl. Phys., vol. 38, pp. 425-428, Jan. 1999.
9. J. A. Wahl, H. Silva, A. Gokirmak, A. Kumar, J. J. Welser, and S. Tiwari, "Write, erase and storage times in nanocrystals memories and the role of infterface states," in IEDM Tech. Dig., 1999, pp. 375-378.
10. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981, pp. 849-850.
11. T. Usuki, T. Futatsugi, and N. Yokoyama, "A proposal of new floating-gate memory storing a small number of electrons with relatively long retention time at low voltage operations," Microelectron. Eng., vol. 47, pp. 281-283, 1999.
12. 2 tunneling dielectrics," IEEE Trans. Electron Devices, vol. 50, pp. 1823-1829, Sept. 2003.
13. 2 high-κ tunneling dielectric," in Proc. VLSI Tech. Symp., vol. 2003, pp. 33-34.
14. C. M. Compagnoni, D. Ielmini, A. S. Spinelli, A. L. Lacaita, C. Gerardi, L. Perniola, B. De Salvo, and S. Lombardo, "Program/erase dynamics and channel conduction in nanocrystal memories," in IEDM Tech. Dig., vol. 2003, pp. 549-552.
15. S. Choi, M. Cho, and H. Hwang, "Improved metal-oxide-nitride-oxide-silicon-type Flash device with high-κ dielectrics for blocking layer," J. Appl. Phys., vol. 8, pp. 5408-5410, Oct. 2003.
16. CRC Handbook of Chemistry and Physics, 70th ed. A ready-Reference Book of Chemical and Physical Data, R. C. Weast, D. R. Lide, M. J. Astle, and W. H. Beyer, Eds., CRC, Boca Raton, Florida, 1990.
17. Y. Q. Wang, J. H. Chen, W. J. Yoo, Y.-C. Yeo, S. J. Kim, R. Gupta, Z. Y. L. Tan, D.-L. Kwong, A. Y. Du, and N. Balasubramanian, "Formation of Ge nanocrystals in HfAlO high-κ dielectric and application in memory device," Appl. Phys. Lett., vol. 84, pp. 5407-5409, Jun. 2004.
18. 3 using atomic layer deposition," Appl. Phys. Lett., vol. 68, pp. 4218-4220, Nov. 2002.
19. 3 laminate gate dielectric and CVD-TaN metal gate deposited by TAIMATA," in IEDM Tech Dig., vol. 2003, pp. 327-330.
20. M. She and T.-J. King, "Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance," IEEE Trans. Electron Devices, vol. 50, pp. 1934-1940, Sept. 2003.
21. Y. M. Niquet, G. Allan, C. Delerue, and M. Lannoo, "Quantum confinement in germanium nanocrystals," Appl. Phys. Lett., vol. 77, pp. 1182-1184, Aug. 2002.
22. D. K. Nayak, J. S. Park, J. C. S. Woo, and K. L. Wang, "Interface properties of thin oxides grown on strained Ge Si layer," J. Appl. Phys., vol. 76, pp. 982-986, Jul. 1994.
23. W. J. Zhu, T.-P. Ma, T. Tamagawa, J. Kim, and Y. Di, "Current transport in metal/hafnium oxide/silicon structure," IEEE Electron Device Lett., vol. 23, pp. 97-99, Feb. 2002.
24. 2 and HfAlO gate stacks," in IEDM Tech. Dig., 2002, pp. 731-734.
25. 2 gate stack," IEEE Electron Device Lett., vol. 25, pp. 123-125, Mar. 2004.
26. C. Lee, Z. Liu, and E. C. Kan, "Investigation on process dependence of self-assembled metal nanocrystals," in Proc. Mater. Res. Soc. Symp., vol. 737, Dec. 2002, pp. F8.18.1-F8.18.6.
27. International Technology Roadmap for Semiconductors. [Online]http:/ /public.itrs.net/