Effects of Interface Traps on Charge Retention Characteristics in Silicon-Quantum-Dot-Based Metal-Oxide-Semiconductor Diodes

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 38, Issue 1 B, 1999, Pages 425-428

  Shi, Yi ^a,c   Saito, Kenichi ^a   Ishikuro, Hiroki ^a   Hiramoto, Toshiro ^a,b  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

^c NANJING UNIVERSITY   (China)

Author keywords

Defect; Interface trap; MOS memory; Silicon quantum dot

Indexed keywords

ANNEALING; CRYSTAL DEFECTS; MOS DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DIODES;

CAPACITANCE-VOLTAGE (C-V) MEASUREMENT; INTERFACE TRAPS;

SEMICONDUCTOR QUANTUM DOTS;

EID: 0032621326     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/JJAP.38.425     Document Type: Article

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