A dither-less all digital PLL for cellular transmitters

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2011, Pages

  Vercesi, L ^a   Fanori, L ^b   De Bernardinis, F ^a   Liscidini, A ^b   Castello, R ^b  

^a Marvell   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALL-DIGITAL PLL; BUILDING BLOCKES; DIGITAL CALIBRATIONS; EMISSION MASK; FRACTIONAL SPURS; FREQUENCY RESOLUTIONS; IN-BAND; LOW LEVEL; LOW-PHASE-NOISE; OUT-OF-BAND; SPUR CANCELLATION; TWO-POINT MODULATION; VERNIER TDC; WIDE-BAND;

FREQUENCY SYNTHESIZERS; INTEGRATED CIRCUIT MANUFACTURE; TRANSMITTERS;

DIGITAL INTEGRATED CIRCUITS;

EID: 80455145095     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2011.6055301     Document Type: Conference Paper

References (26)

1. R. B. Staszewski, P. T. Balsara, "All-Digital Frequency Synthesizer in deep-submicron CMOS", John Wiley & Sons (2006), ISBN: 0-471- 77255-0
2. M. E. Heidari, et al., "All-Digital Outphasing Modulator for a Software-Defined Transmitter," Solid-State Circuits, IEEE Journal of, vol. 44, no. 4, p. 1260-1271, 2009.
3. M. Zanuso, et al., "A Wideband 3.6 GHz Digital Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation," IEEE Journal of Solid-State Circuits, vol. 46, no. 3, p. 627-638, 2011
4. E. Temporiti, et al., "Insights into wideband fractional All- Digital PLLs for RF applications," in Custom Integrated Circuits Conference, 2009. CICC '09. IEEE, 2009, p. 37-44.
5. Kokubo, M et al., "A fast-frequency-switching PLL synthesizer LSI with a numerical phase comparator" in Solid-State Circuits Conference, Digest of Tech. Papers p. 260, Feb. 1995.
6. R. B. Staszewski et al., "All-digital PLL and transmitter for mobile phones," Solid-State Circuits, IEEE Journal of, vol. 40, no. 12, p. 2469-2482, 2005.
7. P. Dudek, S. Szczepanski, and J. V. Hatfield, "A highresolution CMOS time-to-digital converter utilizing a Vernier delay line," IEEE Journal of Solid-State Circuits, vol. 35, no. 2, p. 240-247, 2000. (Pubitemid 30557812)
8. R. Tonietto, et al., "A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter"in 2006 Proceedings of the 32nd European Solid-State Circuits Conference, 2006, p. 150-153.
9. K. Nose et al., "A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling," Solid-State Circuits, IEEE Journal of, vol. 41, no. 12, p. 2911-2920, Dec. 2006. (Pubitemid 44955516)
10. J. Borremans, et al., "A 6fJ/step, 5.5ps time-to-digital converter for a digital PLL in 40nm digital LP CMOS," Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE, p. 417-420, 2010.
11. M. Lee and A. A. Abidi, "A 9 b, 1.25 ps Resolution Coarse- Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue," IEEE Journal of Solid-State Circuits, vol. 43, no. 4, p. 769-777, 2008. (Pubitemid 351464069)
12. M. Z. Straayer et al. "A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping," IEEE Journal of Solid-State Circuits, vol. 44, no. 4, p. 1089-1098, 2009.
13. P. Lu and P. Andreani, "A high-resolution Vernier Gated- Ring-Oscillator TDC in 90-nm CMOS," Norchip, 2010, p. 1-4, 2010.
14. M. Zanuso, et al., "Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 3, p. 548-555, 2010.
15. A. Liscidini, et al., "Time to digital converter based on a 2- dimensions Vernier architecture," in Custom Integrated Circuits Conference, 2009. CICC '09. IEEE, 2009, p. 45-48.
16. L. Vercesi, A. Liscidini, and R. Castello, "Two-Dimensions Vernier Time-to-Digital Converter," IEEE Journal of Solid- State Circuits, vol. 45, no. 8, p. 1504-1512, 2010.
17. R. B. Staszewski, et al., "A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones," Solid-State Circuits, IEEE Journal of, vol. 40, no. 11, p. 2203-2211, Nov. 2005.
18. Y. Chen et al., "A 9 GHz Dual-Mode Digitally Controlled Oscillator for GSM/UMTS Transceivers in 65 nm CMOS" in 2007 IEEE Asian Solid-State Circuits Conference, 2007, p. 432-435.
19. Hung, R., et al., "A Digitally Controlled Oscillator System for SAW-Less Transmitters in Cellular Handsets," Solid-State Circuits, IEEE Journal of, vol. 41, no. 5, p. 1160-1170, May. 2006.
20. I. Bashir, et al., "Tuning Word Retiming of a Digitally- Controlled Oscillator Using RF Built-In Self Test," Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on, p. 103-106, 2006.
21. L. Fanori, et al., "Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning," IEEE Journal of Solid-State Circuits, vol. 45, no. 12, p. 2737-2745, 2010.
22. C. M. Hsu, M. Z. Straayer, M. H. Perrott, "A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise- Shaping Time-to-Digital Converter and Quantization Noise Cancella- tion" IEEE Journal of Solid- State Circuits (2008) vol. 43 (12) pp. 2776-2786
23. J.Borremans, et al.,"A86 MHz-to-12 GHz digital-intensive phase-modulated fractional-N PLL using a 15 pJ/shot 5 ps TDC in 40 nm digital CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 480-481.
24. Xiang Gao, E. et al., "Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 2, p. 117-121, 2009.
25. X. Gao et al., "A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by," Solid-State Circuits, IEEE Journal of, vol. 44, no. 12, p. 3253-3263, 2009.
26. D. Tasca et al., A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power" in Solid-State Circuits Conference, 2011. Digest of Technical Papers. p. 88, Feb. 2011.