A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/shot 5ps TDC in 40nm digital CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 480-481

  Borremans, Jonathan ^a   Vengattaramane, Kameswaran ^a,b   Giannini, Vito ^a   Craninckx, Jan ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS SCALING; DIGITAL CMOS; DIGITAL PHASE MODULATION; ENERGY EFFICIENT; FRACTIONAL-N; LOOP BANDWIDTH; MISMATCH CALIBRATION; RE-CONFIGURABLE;

CALIBRATION; CMOS INTEGRATED CIRCUITS; JITTER; PHASE MODULATION;

PHASE LOCKED LOOPS;

EID: 77952137360     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433840     Document Type: Conference Paper

References (7)

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6. S. Henzler, S. Koeppe, D. Lorenz, W. Kamp, R. Kuenemund, D. Schmitt-Landsiedel, "A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion", J. Solid-State Circuits, vol. 43, no. 7, pp.1666-1676, July 2008.
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