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Volumn , Issue , 2011, Pages 88-89

A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; DIGITAL INTEGRATED CIRCUITS; FREQUENCY CONVERTERS; JITTER; PHASE LOCKED LOOPS; SIGNAL DETECTION;

EID: 79955715979     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746231     Document Type: Conference Paper
Times cited : (60)

References (6)
  • 1
    • 77952162660 scopus 로고    scopus 로고
    • A 3.5GHz Wideband ADPLL with Fractional Spur Suppression through TDC dithering and Feedforward Compensation
    • Feb.
    • C. Weltin-Wu, E. Temporiti, D. Baldi, M. Cusmai, and F. Svelto, "A 3.5GHz Wideband ADPLL with Fractional Spur Suppression through TDC dithering and Feedforward Compensation," ISSCC Dig. Tech. Papers, pp. 468-469, Feb., 2010.
    • (2010) ISSCC Dig. Tech. Papers , pp. 468-469
    • Weltin-Wu, C.1    Temporiti, E.2    Baldi, D.3    Cusmai, M.4    Svelto, F.5
  • 2
    • 77952137360 scopus 로고    scopus 로고
    • A 86MHz-to-12GHz Digital-Intensive Phase-Modulated Fractional-N PLL Using a 15pJ/Shot 5ps TDC in 40nm digital CMOS
    • Feb.
    • J. Borremans, K. Vengattaramane, V. Giannini, and J. Craninckx, "A 86MHz-to-12GHz Digital-Intensive Phase-Modulated Fractional-N PLL Using a 15pJ/Shot 5ps TDC in 40nm digital CMOS," ISSCC Dig. Tech. Papers, pp. 480-481, Feb., 2010.
    • (2010) ISSCC Dig. Tech. Papers , pp. 480-481
    • Borremans, J.1    Vengattaramane, K.2    Giannini, V.3    Craninckx, J.4
  • 3
    • 34548839598 scopus 로고    scopus 로고
    • A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching Scheme
    • Feb.
    • M. Ferris and M. Flynn, "A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching Scheme," ISSCC Dig. Tech. Papers, pp. 352-353, Feb., 2007.
    • (2007) ISSCC Dig. Tech. Papers , pp. 352-353
    • Ferris, M.1    Flynn, M.2
  • 4
    • 77952137361 scopus 로고    scopus 로고
    • A 3MHz-BW 3.6GHz Digital Fractional-N PLL with Sub-gate-delay TDC, Phase-interpolation Divider, and Digital Mismatch Cancellation
    • Feb.
    • M. Zanuso, S. Levantino, C. Samori, A. L. Lacaita, "A 3MHz-BW 3.6GHz Digital Fractional-N PLL with Sub-gate-delay TDC, Phase-interpolation Divider, and Digital Mismatch Cancellation," ISSCC Dig. Tech. Papers, pp. 476-477, Feb., 2010.
    • (2010) ISSCC Dig. Tech. Papers , pp. 476-477
    • Zanuso, M.1    Levantino, S.2    Samori, C.3    Lacaita, A.L.4
  • 5
    • 58049203870 scopus 로고    scopus 로고
    • Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation
    • Dec.
    • N. Da Dalt, "Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation," IEEE Trans. on Circuits and Systems-I, vol. 55, no. 11, pp. 3663-3675, Dec., 2008.
    • (2008) IEEE Trans. on Circuits and Systems-I , vol.55 , Issue.11 , pp. 3663-3675
    • Da Dalt, N.1
  • 6
    • 77956224145 scopus 로고    scopus 로고
    • A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-Band Phase Noise at 700μW Loop-Components Power
    • June
    • X. Gao, E.A.M. Klumperink, G. Socci, M. Bohsali, and B. Nauta, "A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-Band Phase Noise at 700μW Loop-Components Power," IEEE Symp. on VLSI Circuits, pp. 139-140, June, 2010.
    • (2010) IEEE Symp. on VLSI Circuits , pp. 139-140
    • Gao, X.1    Klumperink, E.A.M.2    Socci, G.3    Bohsali, M.4    Nauta, B.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.