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4444331072
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TDC-Based Frequency Synthesizer for Wireless Applications
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Staszewski, R.B.1
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57849164692
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A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation
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Dec
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4444377645
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A 700kHz Bandwidth ΔΣ Fractional Synthesizer With Spurs Compensation and Linearization Techniques for WCDMA Applications
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Sept
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E. Temporiti, G. Albasini, I. Bietti, R. Castello, M. Colombo, "A 700kHz Bandwidth ΔΣ Fractional Synthesizer With Spurs Compensation and Linearization Techniques for WCDMA Applications", IEEE J. Solid-State Circuits, vol. 39, no. 9, Sept. 2004, pp. 1446-1454.
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4
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0027590694
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Delta-Sigma Modulation in Fractional-N Frequency Synthesis
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0742268982
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A wideband 2.4 GHz delta-sigma fractional-N PLL with 1Mb/s in-loop modulation
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Jan
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A Digitally Controlled Oscillator in a 90 nm Digital CMOS Process for Mobile Phones
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Nov
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R. B. Staszewski, C.-M. Hung, N. Barton, M.-C. Lee, and D. Leipold, "A Digitally Controlled Oscillator in a 90 nm Digital CMOS Process for Mobile Phones", IEEE J. Solid-State Circuits, vol. 40, no.11, Nov 2005, pp. 2203-2211.
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7
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51949095217
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A Low Noise, Wideband Digital Phase-locked Loop based on a New Time-to-Digital Converter with Subpicosecond Resolution
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M. Lee, M. E. Heidari, and A. A. Abidi, "A Low Noise, Wideband Digital Phase-locked Loop based on a New Time-to-Digital Converter with Subpicosecond Resolution", Proc. 2008 IEEE Symposium on VLSI Circuits, pp. 112-113.
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8
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61449204062
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A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques
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March
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E. Temporiti, C. Weltin-Wu, D. Baldi, R. Tonietto, and F. Svelto, "A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques", IEEE J. Solid-State Circuits, vol. 44, no.3, March 2009, pp. 824-834.
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9
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46649102037
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Time-Domain Modeling of an RF All-Digital PLL
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June
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I. L. Syllaios, R. B. Staszewski, and P. T. Balsara, "Time-Domain Modeling of an RF All-Digital PLL", IEEE Trans. Circuits and Systems - II: Express Briefs, vol. 55, no.6, June 2008, pp. 601-605.
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10
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0036685487
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A modeling approach for Σ-Δ fractional-N frequency synthesizers allowing straightforward noise analysis
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Aug
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11
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15944399705
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Phase-Domain All-Digital Phase-Locked Loop
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March
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R. B. Staszewski, and P. T. Balsara, "Phase-Domain All-Digital Phase-Locked Loop", IEEE Trans. Circuits and Systems - II: Express Briefs, vol. 52, no.3, March 2005, pp. 159-163.
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46749156902
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A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion
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Jul
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S. Henzler, S. Koeppe, D. Lorenz, W. Kamp, R. Kuenemund, and D. Schmitt-Landsiedel, "A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion," IEEE J. Solid-State Circuits, vol. 43, no. 7, Jul. 2008, pp. 1666-1676.
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13
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A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line
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0021586344
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Full-Speed Testing of A/D Converters
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57849135622
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Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL
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Dec
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K. J. Wang, A. Swaminathan, and I. Galton, "Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL", IEEE J. Solid-State Circuits, vol. 43, no. 12, Dec. 2008, pp. 2787-2797.
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