Effects of channel thickness variation on bias stress instability of InGaZnO thin-film transistors

Microelectronics Reliability

Volumn 51, Issue 9-11, 2011, Pages 1792-1795

  Cho, Edward Namkyu ^a   Kang, Jung Han ^a   Yun, Ilgu ^a  

^a Yonsei University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS STRESS; CARRIER TRAPPING; CHANNEL LAYERS; CHANNEL THICKNESS; COMMERCIAL APPLICATIONS; DEFECT CREATION; ELECTRICAL BIAS; ELECTRICAL CHARACTERISTIC; FREE CARRIERS; GATE BIAS; LAYER THICKNESS; STRESS TIME; THRESHOLD VOLTAGE SHIFTS; TRAP STATE;

EXPONENTIAL FUNCTIONS; THRESHOLD VOLTAGE;

THIN FILM TRANSISTORS;

EID: 80052926528     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2011.07.018     Document Type: Conference Paper

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