Matched public PUF: Ultra low energy security platform

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2011, Pages 45-50

  Meguerdichian, Saro ^a   Potkonjak, Miodrag ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

device aging; hardware security; PPUF; public key cryptography; PUF

Indexed keywords

DEVICE AGING; HARDWARE SECURITY; PPUF; PUBLIC KEYS; PUF;

LOW POWER ELECTRONICS; POWER ELECTRONICS; PUBLIC KEY CRYPTOGRAPHY;

NETWORK SECURITY;

EID: 80052734604     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISLPED.2011.5993602     Document Type: Conference Paper

References (28)

1. F. Dabiri and M. Potkonjak, "Hardware aging-based software metering," DATE, pp. 260-465, 2009.
2. M. Nelson et al., "SVD-based ghost circuitry detection," IH, 2009.
3. F. Koushanfar and M. Potkonjak, "CAD-based security, cryptography, and digital rights management," DAC, pp. 268-269, 2007. (Pubitemid 47129968)
4. Y. Alkabani et al., "Remote activation of ICs for piracy prevention and digital right management," ICCAD, pp. 674-677, 2007.
5. A. R. Brown, V. Huard, and A. Asenov, "Statistical simulation of progressive NBTI degradation in a 45-nm technology pMOSFET," T-ED, vol. 57, no. 9, pp. 2320-2323, 2010.
6. S. Smith et al., "Comparison of measurement techniques for linewidth metrology on advanced photomasks," SM, vol. 22, no. 1, pp. 72-79, 2009.
7. J. S. J. Wong, P. Sedcole, and P. Y. K. Cheung, "Self- Characterization of combinatorial circuit delays in FPGAs," ICFPT, pp. 245-251, 2007.
8. A. Keshavarzi, et al., "Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage," ISLPED, pp. 26-29, 2005. (Pubitemid 41731620)
9. S. Wei et al., "Gate-level characterization: foundations and hardware security applications," DAC, pp. 222-227, 2010.
10. M. Potkonjak et al., "Hardware Trojan horse detection using gate-level characterization," DAC, pp. 688-693, 2009.
11. S. Wei, S. Meguerdichian, and M. Potkonjak, "Malicious circuitry detection using thermal conditioning," IEEE TIFS, 2011.
12. A. Vahdatpour et al., "A gate level sensor network for integrated circuits temperature monitoring," IEEE Sensors, pp. 652-655, 2010.
13. B. Cline, K. Chopra, D. Blaauw, and Y. Cao, "Analysis and modeling of CD variation for statistical static timing," ICCAD, pp. 60-66, 2006.
14. M. A. Alam and S. Mahapatra, "A comprehensive model of PMOS NBTI degradation," Microelectronics Reliability, vol. 45, pp. 71-81, 2005.
15. R. Pappu, B. Recht, J. Taylor, and N. Gershenfeld, "Physical one-way functions," Science, vol. 297, no. 5589, pp. 2026-2030, 2002.
16. B. Gassend, D. Clarke, M. van Dijk, and S. Devadas, "Silicon physical random functions," CCS, pp. 148-160, 2002.
17. N. Beckmann and M. Potkonjak, "Hardware-based public-key cryptography with public physically unclonable functions," IH, pp. 206-220, 2009.
18. U. Rührmair, "SIMPL systems, or: can we design cryptographic hardware without secret key information?" SOFSEM, vol. 6543, pp. 26-45, 2011.
19. M. Potkonjak et al., "Differential public physically unclonable functions: architecture and applications," DAC, 2011.
20. M. Potkonjak, S. Meguerdichian, and J. L. Wong, "Trusted sensors and remote sensing," IEEE Sensors, pp. 1104-1107, 2010.
21. M. Majzoobi, F. Koushanfar, and M. Potkonjak, "Lightweight secure PUFs," ICCAD, pp. 670-673, 2008.
22. S. Meguerdichian and M. Potkonjak, "Device aging-based physically unclonable functions," DAC, 2011.
23. S. Meguerdichian, "Device aging-based PPUFs: architecture and protocols," M.S. thesis, Computer Science Dept., UCLA, 2011.
24. D. Markovic et al., "Ultralow-power design in near-threshold region," Proceedings of the IEEE, vol. 98, no. 2, pp. 237-252, 2010.
25. S. Sarangi et al., "VARIUS: a model of process variation and resulting timing errors for microarchitects." SM, vol. 21, no. 1, pp. 3-13, 2008. (Pubitemid 351229812)
26. A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 um MOSFETs: a 3-D atomistic simulation study," T-ED, vol. 45, no. 12, pp. 2505-2513, 1998. (Pubitemid 128736693)
27. S. Chakravarthi et al., "A comprehensive framework for predictive modeling of negative bias temperature instability," IRPS, pp. 273-282, 2004.
28. T. Good and M. Benaissa, "692-nW advanced encryption standard (AES) on a 0.13-μm CMOS," VLSI, vol. 18, no. 12, pp. 1753-1757, 2010.