A novel table-based approach for design of FinFET circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 7, 2009, Pages 1061-1070

  Thakker, Rajesh A ^a   Sathe, Chaitanya ^b   Sachid, Angada B ^a   Shojaei Baghini, Maryam ^a   Ramgopal Rao, V ^a,c   Patil, Mahesh B ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b University of Illinois at Urbana Champaign   (United States)

^c Indian Academy of Sciences   (India)

Author keywords

Circuit design; FinFET; Hierarchical particle swarm optimization (PSO); Lookup table (LUT)

Indexed keywords

CIRCUIT DESIGN; CIRCUIT SIMULATORS; COMPACT MODEL; EFFICIENT DESIGNS; FINFET; HIERARCHICAL PARTICLE SWARM OPTIMIZATION (PSO); IN-PROCESS; LOOK UP TABLE; LOOKUP TABLE (LUT); MIXED MODE; MOS TRANSISTORS; OPTIMIZER; SIMULATION RESULT; SUPPLY VOLTAGES;

CIRCUIT SIMULATION; DESIGN; DRAIN CURRENT; ELECTRIC POTENTIAL; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT MANUFACTURE; TABLE LOOKUP; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

PARTICLE SWARM OPTIMIZATION (PSO);

EID: 67650917099     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2017431     Document Type: Article

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