-
1
-
-
2442653861
-
How scaling will change processor architecture
-
Horowitz et al., "How scaling will change processor architecture." ISSCC, 2004.
-
(2004)
ISSCC
-
-
Horowitz1
-
2
-
-
13644284230
-
A perspective from the 2003 ITRS: MOSFET scaling trends, challenges, and potential solutions
-
Zeitzoff et al., "A perspective from the 2003 ITRS: MOSFET scaling trends, challenges, and potential solutions." CDM, 2005.
-
(2005)
CDM
-
-
Zeitzoff1
-
3
-
-
33748535403
-
High-performance cmos variability in the 65-nm regime and beyond
-
Bernstein et al., "High-performance cmos variability in the 65-nm regime and beyond." IBM-JRD, 2006.
-
(2006)
IBM-JRD
-
-
Bernstein1
-
4
-
-
0031077147
-
Analysis and decomposition of spatial variation in integrated circuit processes and devices
-
Stine et al., "Analysis and decomposition of spatial variation in integrated circuit processes and devices." TSM, 1997.
-
(1997)
TSM
-
-
Stine1
-
5
-
-
50249144251
-
Using a statistical metrology framework to identify random and systematic sources of intra-die ILD thickness variation for CMP processes
-
Chang et al., "Using a statistical metrology framework to identify random and systematic sources of intra-die ILD thickness variation for CMP processes." IEDM, 1995.
-
(1995)
IEDM
-
-
Chang1
-
6
-
-
77953110760
-
Analysis of polysilicon critical dimension variation for submicron CMOS processes
-
Dept.of ECE
-
Fitzgerald et al., "Analysis of polysilicon critical dimension variation for submicron CMOS processes." MIT, Dept.of ECE, 1994.
-
(1994)
MIT
-
-
Fitzgerald1
-
7
-
-
77953089402
-
Manufacturability evaluation of deep submicron exposure tools using statistical metrology
-
Yu et al., "Manufacturability evaluation of deep submicron exposure tools using statistical metrology." ISSM, 1995.
-
(1995)
ISSM
-
-
Yu1
-
8
-
-
84886474055
-
Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS
-
Chen et al., "Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS." VTS, 2005.
-
(2005)
VTS
-
-
Chen1
-
9
-
-
33745209228
-
An extended model for optimal burn-in procedures
-
J. H. Cha et al., "An extended model for optimal burn-in procedures." TR, 2006.
-
(2006)
TR
-
-
Cha, J.H.1
-
10
-
-
0348040085
-
Statistical timing analysis for intra-die process variations with spatial correlations
-
Agarwal et al., "Statistical timing analysis for intra-die process variations with spatial correlations." ICCAD, 2003.
-
(2003)
ICCAD
-
-
Agarwal1
-
11
-
-
70350357187
-
False path aware timing yield estimation under variability
-
Xie et al., "False path aware timing yield estimation under variability." VTS, 2009.
-
(2009)
VTS
-
-
Xie1
-
12
-
-
57849143764
-
Process variability-aware transient fault modeling and analysis
-
Miskov et al., "Process variability-aware transient fault modeling and analysis." ICCAD, 2008.
-
(2008)
ICCAD
-
-
Miskov1
-
13
-
-
49749120178
-
Transistor-specific delay modeling for ssta
-
Cline et al., "Transistor-specific delay modeling for ssta." DATE, 2008.
-
(2008)
DATE
-
-
Cline1
-
14
-
-
33748329641
-
First-order incremental block-based statistical timing analysis
-
Visweswariah et al., "First-order incremental block-based statistical timing analysis." TCAD-ICS, 2006.
-
(2006)
TCAD-ICS
-
-
Visweswariah1
-
15
-
-
33750596850
-
Reversed temperature-dependent propagation delay characteristics in nanometer cmos circuits
-
Kumar et al., "Reversed temperature-dependent propagation delay characteristics in nanometer cmos circuits." TCS, 2006.
-
(2006)
TCS
-
-
Kumar1
-
16
-
-
38949186007
-
VARIUS: A model of process variation and resulting timing errors for microarchitects
-
Sarangi et al., "VARIUS: A model of process variation and resulting timing errors for microarchitects." TSM, 2008.
-
(2008)
TSM
-
-
Sarangi1
-
17
-
-
28444470490
-
Performance, energy, and thermal considerations for smt and cmp architectures
-
Yingmin et al., "Performance, energy, and thermal considerations for smt and cmp architectures." HPCA, 2005.
-
(2005)
HPCA
-
-
Yingmin1
-
19
-
-
13144266757
-
A process-tolerant cache architecture for improved yield in nanoscale technologies
-
Agarwal et al., "A process-tolerant cache architecture for improved yield in nanoscale technologies." TVLSI, 2005.
-
(2005)
TVLSI
-
-
Agarwal1
-
20
-
-
40349098498
-
Mitigating the impact of process variations on processor register files and execution units
-
Liang et al., "Mitigating the impact of process variations on processor register files and execution units." MICRO, 2006.
-
(2006)
MICRO
-
-
Liang1
-
21
-
-
0030149507
-
CACTI: An enhanced cache access and cycle time model
-
Wilton et al., "CACTI: An enhanced cache access and cycle time model." JSSC, 1996.
-
(1996)
JSSC
-
-
Wilton1
-
23
-
-
77953111122
-
Predictive technology model for nano-cmos design exploration
-
W. Zhao and Y. Cao, "Predictive technology model for nano-cmos design exploration." JECTS, 2007.
-
(2007)
JECTS
-
-
Zhao, W.1
Cao, Y.2
-
24
-
-
84932168626
-
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation
-
Liu et al., "Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation." ISPLED, 2004.
-
(2004)
ISPLED
-
-
Liu1
|