N3ASICs: Designing nanofabrics with fine-grained CMOS integration

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011

Volumn , Issue , 2011, Pages 196-202

  Panchapakeshan, Pavan ^a   Narayanan, Pritish ^a   Moritz, Csaba Andras ^a  

^a University of Massachusetts   (United States)

Author keywords

3 D integration; N3ASIC; nano CMOS hybrid system; nanowires; NASIC

Indexed keywords

3-D INTEGRATION; ACTIVE DEVICES; CAD TOOL; CMOS DESIGN; CMOS INTEGRATION; CMOS MANUFACTURING; DESIGN RULES; FABRIC DESIGN; KEY SYSTEMS; LAYER-BY-LAYER ASSEMBLIES; MANUFACTURING CONSTRAINT; METAL INTERCONNECTS; NANO CMOS; NANO-MANUFACTURING; NANOFABRICS; NASIC; POWER EFFICIENT; SCALED CMOS; SEMICONDUCTOR NANOWIRE;

HYBRID SYSTEMS; MANUFACTURE; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; NANOWIRES; SEMICONDUCTOR DEVICES; THREE DIMENSIONAL;

COMPUTER AIDED DESIGN;

EID: 79961180326     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANOARCH.2011.5941504     Document Type: Conference Paper

References (31)

1. T. Wang, P. Narayanan, and C. Andras Moritz, "Heterogeneous Two-Level Logic and Its Density and Fault Tolerance Implications in Nanoscale Fabrics," IEEE Transactions on Nanotechnology, vol. 8, no. 1, pp. 22-30, Jan. 2009.
2. C. A. Moritz et al., "Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 11, pp. 2422-2437, Nov. 2007.
3. P. Narayanan, M. Leuchtenburg, T. Wang, and C. A. Moritz, "CMOS Control Enabled Single-Type FET NASIC," in 2008 IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, 2008, pp. 191-196.
4. C. A. Moritz, P. Narayanan, and C. O. Chui, Nanoscale Application Specflc Integrated Circuits.
5. T. Wang, P. Narayanan, and C. A. Moritz, "Combining 2-level logic families in grid-based nanoscale fabrics," in 2007 IEEE International Symposium on Nanoscale Architectures, San Jose, CA, USA, 2007, pp. 101-108.
6. P. Narayanan, K. W. Park, C. O. Chui, and C. A. Moritz, "Manufacturing pathway and associated challenges for nanoscale computational systems," in Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, 2009, pp. 119-122.
7. K. K. Likharev, "CMOL: Second life for silicon?," Microelectronics Journal, vol. 39, p. 177-183, Feb. 2008.
8. G. S. Snider and R. S. Williams, "Nano/CMOS architectures using a field-programmable nanowire interconnect," Nanotechnology, vol. 18, no. 3, p. 035204, Jan. 2007.
9. "2009 ITRS." [Online]. Available: http://www.itrs.net/Links/ 2009ITRS/Home2009.htm.
10. T. Mårtensson, P. Carlberg, M. Borgström, L. Montelius, W. Seifert, and L. Samuelson, "Nanowire Anays Defined by Nanoimprint Lithography," Nano Letters, vol. 4, no. 4, pp. 699-702, Apr. 2004.
11. C. Picciotto, J. Gao, Z. Yu, and W. Wu, "Alignment for imprint lithography using nDSE and shallow molds," Nanotechnology, vol. 20, no. 25, p. 255304, Jun. 2009.
12. D. Wang, Y. Bunimovich, A. Boukai, and J. R. Heath, "Two-dimensional single-crystal nanowire arrays," Dec-2007. [Online]. Available: http://www.nanoarchive.org/1853/.
13. D. Wang, B. A. Sheriff, M. McAlpine, and J. R. Heath, "Development of ultra-high density silicon nanowire anays for electronics applications," Nano Research, vol. 1, no. 1, pp. 9-21, Jul. 2008.
14. J. R. Heath, "Superlattice Nanowire Pattern Transfer (SNAP)," Accounts of Chemical Research, vol. 41, no. 12, pp. 1609-1617, Dec. 2008.
15. C. Bencher, H. Dai, and Y. Chen, "Gridded design rule scaling: taking the CPU toward the 16nm node," in Proceedings of SPIE, San Jose, CA, USA, 2009, p. 72740G-72740G-10.
16. S. H. Zaidi, "Moire interferometric alignment and overlay techniques," in Proceedings of SPIE, San Jose, CA, USA, 1994, pp. 371-382.
17. Supratik Guha and Vijay Narayanan, "High-κ/Metal Gate Science and Technology," 06-Jul-2009. [Online]. Available: http://www. annualreviews.org/doi/abs/10.1146/annurev-matsci-082908-145320.
18. C. Pacha et al., "Circuit design issues in multi-gate FET CMOS technologies," in 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, San Francisco, CA, 2006, pp. 1656-1665.
19. P. Narayanan, C. A. Moritz, K. W. Park, and C. O. Chui, "Validating cascading of crossbar circuits with an integrated device-circuit exploration," in 2009 IEEE/ACM International Symposium on Nanoscale Architectures, San Francisco, CA, USA, 2009, pp. 37-42.
20. P. Narayanan, J. Kina, P. Panchapakeshan, C. O. Chui, and C. A. Moritz, "Integrated Device-Fabric explorations and Noise Mitigation in Nanoscale Fabrics," Submitted to TNANO under review.
21. T. Wang, "Fault tolerant nanoscale microprocessor design on semiconductor nanowire grids," University of Massachusetts, Amherst.
22. "Synopsys- Sentaurus User Guide," 2009.
23. Streetman and Banerjee, Solid state electronic devices, 6th ed. Englewood Cliffs, NJ: Prentice-Hall, 2010.
24. "HSPICE Simulation and Analysis Guide," 2009.
25. W. Zhao and Y. Cao, "New Generation of Predictive Technology Model for Sub-45nm Design Exploration," in Proceedings of the 7th International Symposium on Quality Electronic Design, 2006, pp. 585-590.
26. "Predictive Technology Model (PTM)." [Online]. Available: http://ptm.asu.edu/.
27. T. Wang, M. Ben-naser, Y. Guo, and C. A. Moritz, "Wire-streaming processors on 2-D nanowire fabrics," IN NANOTECH 2005. NANO SCIENCE AND TECHNOLOGY INSTITUTE, 2005.
28. V. Chan et al., "Strain for CMOS performance improvement," in Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005., San Jose, CA, USA, pp. 662-669.
29. J.-P. Colinge et al., "Nanowire transistors without junctions," Nat Nano, vol. 5, no. 3, pp. 225-229, Mar. 2010.
30. C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J.-P. Colinge, "Junctionless multigate field-effect transistor," Applied Physics Letters, vol. 94, no. 5, p. 053511, 2009.
31. B. Zahiri, "Structured ASICs: opportunities and challenges," in Proceedings 21st International Conference on Computer Design, San Jose, CA, USA, pp. 404-409.