Fault-tolerant nanoscale processors on semiconductor nanowire grids

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 11 SPEC. ISS., 2007, Pages 2422-2437

  Moritz, Csaba Andras ^a,b   Wang, Teng ^a   Narayanan, Pritish ^a   Leuchtenburg, Michael ^a   Guo, Yao ^a,c   Dezan, Catherine ^a,d   Bennaser, Mahmoud ^a  

^a University of Massachusetts   (United States)

^b BlueRISC Inc   (United States)

^c PEKING UNIVERSITY   (China)

^d UNIVERSITÉ DE BRETAGNE OCCIDENTALE   (France)

Author keywords

Defect tolerance; Fault tolerance; Nanoscale application specific integrated circuit (NASIC); Nanoscale fabrics; Nanoscale processors; Semiconductor nanowires (NWs)

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEFECTS; ERRORS; MANUFACTURE; NANOELECTRONICS; NANOWIRES; REDUNDANCY; SEMICONDUCTOR DEVICES;

DEFECT TOLERANCE; NANO SCALE; NANOSCALE APPLICATIONS; NANOSCALE PROCESSORS; SEMICONDUCTOR NANOWIRE;

FAULT TOLERANCE;

EID: 51849142177     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.907839     Document Type: Article

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