Circuit design issues in multi-gate FET CMOS technologies

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Pacha, Christian ^a   Von Arnim, Klaus ^a   Schulz, Thomas ^a,c   Xiong, Weize ^b,c   Gostkowski, Michael ^c   Knoblinger, Gerhard ^d   Marshall, Andrew ^b   Nirschl, Thomas ^a   Berthold, Joerg ^a   Russ, Christian ^a   Gossner, Harald ^a   Duvvury, Charvaka ^b   Patruno, Paul ^e   Cleavelin, Rinn ^b   Schruefer, Klaus ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b TEXAS INSTRUMENTS   (United States)

^c ATDF   (United States)

^d INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

^e PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUIT PERFORMANCE; GATE LENGTHS;

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ENERGY DISSIPATION; FIELD EFFECT TRANSISTORS; LEAKAGE CURRENTS; OPERATIONAL AMPLIFIERS;

INTEGRATED CIRCUIT LAYOUT;

EID: 39549102528     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)