Combining 2-level logic families in grid-based nanoscale fabrics

2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH

Volumn , Issue , 2007, Pages 101-108

  Wang, Teng ^a   Narayanan, Pritish ^a   Moritz, Csaba Andras ^a  

^a University of Massachusetts   (United States)

Author keywords

CMOL; Nanofabrics; Nanoscale processors; NASIC; Semiconductor nanowires

Indexed keywords

COMPUTATION THEORY; DEFECTS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; NANOTECHNOLOGY;

CMOL; NANOFABRICS; NANOSCALE PROCESSORS; NASIC; SEMICONDUCTOR NANOWIRE;

COMPUTER CIRCUITS;

EID: 50849092521     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANOARCH.2007.4400864     Document Type: Conference Paper

References (21)

1. Y, Cui, X, Duan, J. Hu, and CM. Lieber. "Doping and electrical transport in silicon nanowires", J. Phys. Chem. B, vol. 104, no. 22, pp. 5213-5216, June 2000
2. Y. Huang, X. Duan, Y. Cui, L.J. Lauhon, K-Y. Kim, and C. M. Lieber, "Logic Gates and Computation from Assembled Nanowire Building Blocks", Science, vol. 294, no. 5545, pp. 1313-1317, November 2001.
3. Y. Huang, X. Duan, Q. Wei, and C. M. Lieber, "Directed Assembly of One-Dimensional Nanostructures into Functional Networks", Science, vol. 291, no. 5504, pp. 630-633, January 2001.
4. Y. Wu, J. Xiang, C. Yang, W. Lu and C. M. Lieber, "Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures", Nature, vol. 430, pp. 61-65, July 2004.
5. A. DeHon. "Nanowire-based Programmable Architectures", ACM Journal on Emerging Technologies in Computing Systems, vol. 1, no. 2, pp. 109-162, July 2005.
6. K.K. Likharev, D.B. Strukov, "CMOL; Devices, Circuits, and Architectures. Introducing Molecular Electronics", in Lecture Notes in Physics, vol. 680, pp. 447-477, 2005.
7. C.A. Moritz, T. Wang, P. Narayanan, M. Leucntenburg, Y. Guo, C. Dezan, and M, Bennaser, "Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids", IEEE Trans. on Circuits and Systems I, special issue on Nanoeleclronic Circuits and Nanoarchileclures, in press
8. C.A. Moritz and T. Wang, "Towards Defect-tolerant nanoscale architectures", in Proceedings of the 6th IEEE Conference on Nanotechnology, IEEẼNano 2006, vol, l, pp, 331-334, June 2006
9. T. Wang, M. Bennaser, Y. Guo, C.A. Moritz, "Combining Circuit Level and System Level Techniques for Defect-Tolerant Nanoscale Architectures", in Proceedings of the 2nd IEEE International Workshop on Defect and Fault Tolerant Nanoscale Architectures (NanoArch), Boston, MA, June 2006
10. C.A. Moritz and T. Wang, "Latching on the wire and pipelining in nanoscale designs", in Proceedings of the 3rd Non-Silicon Computing Workshop (NSC-3), Munich, Germany, 2004.
11. T. Wang, Z. Qi and C.A. Moritz. "Opportunities and Challenges in Application-tuned Circuits and Architectures Based on Nanodevices", in Proceedings of the 1st ACM International Conference on Computing Frontiers, pp. 503-511, Ischia, Italy, 2004.
12. D. Whang, S. Jin, Y. Wu, and C. M. Lieber. "Large-scale hierarchical organization of nanowire arrays for integrated nanosystems". Nanolellers vol 3, pp. 1255-1259, September 2003.
13. T. Wang, M. Bennaser, Y. Guo and C.A. Moritz, "Wire-Streaming Processors on 2-D Nanowire Fabrics", in Proceedings of Nanotech 2005, Nano Science and Technology Institute, vol. 2, pp. 619-622, Anaheim, CA, 2005.
14. P. Narayanan, M. Leuchtenburg, T. Wang, C.A. Moritz, "CMOS-Control Enabled Single-Type FET NASIC", unpublished.
15. D. B. Strukov and KL.KL. Likharev, "Defect-Tolerant Architecture for Nanoelectronic Crossbar Memories", Journal of Nanoscience and Nanotechnology, special issue on Nanotechnology for Information Storage, vol. 7, no. l, pp. 151-167, January 2006
16. Y.W. Heo, L.C. Tien, Y. Kwon, D.P. Norton, S.J. Pearton, B.S. Kang and F. Ren, "Depletion-mode ZnO nanowire field-effect transistor", Applied Physics Letters, vol. 85, issue 12, pp. 2274-2276, September 2004
17. R.E. Lyions and W. Vanderkulk, "The use of triple modular redundancy to improve computer reliability", IBM Journal of Research and Development, vol. 6, no. 2, pp. 200-209, April 1962.
18. Y. Luo, C. P. Collier, J.O. Jeppesen, K.A. Nielsen, E. Delonno, G. Ho, J. Perkins, H. Tseng, T. Yamamoto, J.F. Stoddart, J.R. Heath, "Two- Dimensional Molecular Electronics Circuits", ChemPhysChem, vol. 3, issue 6, pp. 519-525, 2002.
19. A.B. Greytak, L.J. Lauhon, M.S. Gudiksen, and CM. Lieber, "Growth and transport properties of complementary germanium nanowire field-effect transistors", Applied Physics Letters, vol. 84, no. 21, pp. 4176-4178, May 2004.
20. H.T. Ng, J. Han, T. Yamada, P. Nguyen, Y.P. Chen, and M. Meyyappan, "Single Crystal Nanowire Vertical Surround-Gate Field-Effect Transistor", Nano Letters, vol. 4, no. 7, pp. 1247-1252, May 2004.
21. W. Lu and CM. Lieber, "Semiconductor Nanowires," J. Phys. D: Appl. Physics, vol. 39, pp. R387-R406, October 2006.