Technology assessment methodology for complementary logic applications based on energy-delay optimization

IEEE Transactions on Electron Devices

Volumn 58, Issue 8, 2011, Pages 2430-2439

  Wei, Lan ^a   Oh, Saeroonter ^b   Wong, H S Philip ^c  

^a Massachusetts Institute of Technology Cambridge   (United States)

^b LG Display Co Ltd   (South Korea)

^c Stanford University   (United States)

Author keywords

Complementary metal oxide semiconductor (CMOS); delay; energy; technology assessment

Indexed keywords

ACTIVITY FACTOR; ADVANCED TECHNOLOGY; ASSESSMENT METHODOLOGIES; CARBON NANOTUBE FET; COMPLEMENTARY LOGIC; COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; DELAY; DEVICE STRUCTURES; DEVICE TECHNOLOGIES; ENERGY; ENERGY-DELAY; ENERGY-DELAY OPTIMIZATION; FAN-OUT; FREE VARIABLE; I-V AND C-V CHARACTERISTICS; INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS; LOGIC DEPTH; METAL-OXIDE; MOSFETS; OFF-STATE CURRENT; OPTIMAL SETS; SEMICONDUCTOR FIELD-EFFECT TRANSISTORS; SUPPLY VOLTAGES; TECHNOLOGY ASSESSMENTS; TECHNOLOGY NODES; TUNNELING FET;

DIELECTRIC DEVICES; ENERGY EFFICIENCY; EQUIPMENT; MESFET DEVICES; MOSFET DEVICES; NANOTUBES; OPTIMIZATION; RATING; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; SILICON; TRANSISTORS; VANADIUM;

TECHNOLOGY;

EID: 79960842855     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2157349     Document Type: Article

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