Leakage reduction at architectural level

2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06

Volumn , Issue , 2006, Pages

  Piguet, Christian ^a   Schuster, Christian ^b   Nagel, Jean Luc ^c  

^a EPFL   (Switzerland)

^b UNIVERSITY OF NEUCHÂTEL   (Switzerland)

^c CSEM   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC POWER UTILIZATION; ENERGY DISSIPATION;

ARCHITECTURE COMPARISON; MULTIPLIER; SUBMICRON TECHNOLOGIES;

LEAKAGE CURRENTS;

EID: 37649032541     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2006.220780     Document Type: Conference Paper

References (9)

1. M. Belleville, Olivier Faynot, "Evolution of deep submicron bulk and SOI technologies", Chapter 2, in "Low Power Electronics Design", edited by C. Piguet, CRC Press, 2005
2. K. Roy, A. Agarwal, C. H. Kim. "Circuit Techniques for Leakage Reduction", Chapter 13, in "Low Power Electronics Design", edited by C. Piguet, CRC Press, 2005
3. R.W. Brodersen, et al., "Methods for True Power Minimization", Proceedings of the Int'l Conf. on Computer Aided Design, (2002) November, pp. 35-42. San Jose, California
4. K. Nose, T. Sakurai, "Optimization of Vdd and Vth for Low-Power and High-Speed Applications", Proceedings of the Asia and South Pacific Design Automation Conference, (2000) January 25-28, pp. 469-474; Yokohama, Japan
5. nd
6. Northeast Workshop on Circuits and Systems NewCAS'04, June 20-23, 2004, Montréal, Canada
7. C. Schuster, J-L. Nagel, C. Piguet, P-A. Farine, "Leakage reduction at the architectural level and its application to 16 bit multiplier architectures", PATMOS '04, Santorini Island, Greece, September 15-17,2004
8. C. Schuster, J-L. Nagel, P-A, C. Piguet. Farine, "An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth", Journal of Low-Power Electronics (JOLPE), Vol. 1, No. 1, April 2005, pp. 1-8.
9. C. Schuster, J-L. Nagel, C. Piguet, P-A. Farine, "Architectural and Technology Influence on the Optimal Total Power Consumption", DATE 2006, Munchen, March 6-10, 2006.