Layout scaling of Si1-xGex-channel pFETs

IEEE Transactions on Electron Devices

Volumn 58, Issue 8, 2011, Pages 2544-2550

  Eneman, Geert ^a,b,c   Yamaguchi, Shinpei ^a   Ortolland, Claude ^d   Takeoka, Shinji ^a   Kobayashi, Masaharu ^d,e   Witters, Liesbeth ^a   Hikavyy, Andriy ^a   Mitard, Jérôme ^a   Loo, Roger ^a   Hoffmann, Thomas ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c RESEARCH FOUNDATION FLANDERS FWO   (Belgium)

^d IBM   (United States)

^e STANFORD UNIVERSITY   (United States)

Author keywords

MOS devices; MOSFETs; semiconductor device modelling; semiconductor epitaxial layers; silicon germanium; stress

Indexed keywords

CHANNEL MOBILITY; CHANNEL THICKNESS; CURRENT ENHANCEMENT; DESIGN COMPLEXITY; ELECTRICAL MEASUREMENT; GERMANIUM CONCENTRATION; MOSFETS; NARROW WIDTH; SEMICONDUCTOR DEVICE MODELLING; SEMICONDUCTOR EPITAXIAL LAYERS; SILICON GERMANIUM; TECHNOLOGY COMPUTER AIDED DESIGN; TRANSISTOR WIDTH; WAFER BENDING; WORK FOCUS;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; FIELD EFFECT TRANSISTORS; GERMANIUM; MOS DEVICES; SEMICONDUCTOR DEVICE MODELS; SILICON WAFERS; TRANSISTORS;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 79960842549     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2157507     Document Type: Article

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