Compact modeling of stress effects in scaled CMOS

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn , Issue , 2009, Pages

  Wang, Chi Chao ^a   Zhao, Wei ^a   Liu, Frank ^b   Chen, Min ^a   Cao, Yu ^a  

^a Arizona State University   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

Compact modeling; Layout dependence; Mobility; Stress effect; Threshold voltage

Indexed keywords

90 NM TECHNOLOGY NODE; CHANNEL LENGTH; CMOS TECHNOLOGY; COMPACT MODEL; COMPACT MODELING; DIFFUSION LENGTH; LAYOUT DEPENDENCE; NONUNIFORM STRESS DISTRIBUTION; SCALED CMOS; STANDARD CMOS PROCESS; STRAINED-SI; STRESS EFFECTS;

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; POWDERS; SEMICONDUCTOR DEVICES; STRESS CONCENTRATION; THRESHOLD VOLTAGE; TRANSPORT PROPERTIES;

CARRIER MOBILITY;

EID: 74349095855     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2009.5290231     Document Type: Conference Paper

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