20nm gate length trigate pFETs on strained SGOI for high performance CMOS

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2010, Pages 37-38

  Hutin, L ^a   Casse M ^a   Le Royer, C ^a   Damlencourt, J F ^a   Pouydebasque, A ^a   Xu, C ^a   Tabone, C ^a   Hartmann, J M ^a   Carron, V ^a   Grampeix, H ^a   Mazzocchi, V ^a   Truche, R ^a   Weber, O ^a   Batude, P ^a   Garros, X ^a   Clavelier, L ^a   Vinet, M ^a   Faynot, O ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE AREA; ELASTIC STRAIN RELAXATION; ELECTROSTATIC INTEGRITY; GATE LENGTH; HIGH-PERFORMANCE CMOS; METAL GATE; P-MOSFETS; SIGE ON INSULATOR; TRIGATE; UNIAXIAL STRESS;

HOLE MOBILITY; SILICON ALLOYS;

SEMICONDUCTOR INSULATOR BOUNDARIES;

EID: 77957872502     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2010.5556130     Document Type: Conference Paper

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