3D stacked chip technology using bottom-up electroplated TSVs

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2009, Pages 1177-1184

  Chang, H H ^a,b   Shih, Y C ^a   Hsiao, Z C ^a   Chiang, C W ^a   Chen, Y H ^a   Chiang, K N ^b  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING TECHNOLOGY; BOTTOM ELECTRODES; BOTTOM-UP ELECTROPLATING; CHIP STACKING; CHIP TECHNOLOGY; DRY ETCHING PROCESS; ELECTRICAL CONNECTION; ETCHING PROCESS; HIGH TEMPERATURE PROCESS; LOW COSTS; MOCVD; PROCESS COSTS; PROCESS FLOWS; PROCESS TIME; PROCESS YIELD; RESISTANCE MEASUREMENT; SEED LAYER; SEM; SN BUMPS; THERMAL RELEASE; THERMAL-SHOCK RELIABILITY TESTS; THIN WAFERS; THROUGH-SILICON-VIA; VOID-FREE; WAFER THINNING; WAFER-THINNING PROCESS; X-RAY IMAGE;

ASPECT RATIO; CHEMICAL VAPOR DEPOSITION; COMPRESSIVE STRENGTH; CRACKS; ELECTRIC CONNECTORS; ELECTRONICS PACKAGING; ELECTROPLATING; METALS; PLASMA ETCHING; SILICON WAFERS; SUBSTRATES; TECHNOLOGY; THREE DIMENSIONAL; TIN; X RAY ANALYSIS; X RAY APPARATUS;

WAFER BONDING;

EID: 70349678255     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074161     Document Type: Conference Paper

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