Studying the impact of hardware prefetching and bandwidth partitioning in Chip-MultiProcessors

Performance Evaluation Review

Volumn 39, Issue 1 SPEC. ISSUE, 2011, Pages 37-48

  Liu, Fang ^a   Solihin, Yan ^a  

^a North Carolina State University   (United States)

Author keywords

Analytical model; Chip multiprocessors; Hardware prefetching; Memory bandwidth partitioning

Indexed keywords

BANDWIDTH; COMPUTER AIDED DESIGN; MULTIPROCESSING SYSTEMS; SYSTEMS ANALYSIS;

BANDWIDTH PARTITIONING; CHIP MULTIPROCESSOR; HARDWARE PREFETCHING; IN-CHIP; MEMORY BANDWIDTH PARTITIONING; MEMORY BANDWIDTHS; MODERN HIGH PERFORMANCE; MULTI PROCESSOR SYSTEMS; PREFETCHING; SYSTEMS PERFORMANCE;

ANALYTICAL MODELS;

EID: 79960188403     PISSN: 01635999     EISSN: None     Source Type: Journal    
DOI: 10.1145/2007116.2007121     Document Type: Conference Paper

References (35)

1. A. Snavely and D.M. Tullsen. Symbiotic Job Scheduling for a Simultaneous Multithreading Processor. In Proc. of 19th Intl. Conf. on Architecture Support for Programming Language and Operating Systems(ASPLOS), 2000.
2. B. Sinharoy and R.N. Kalla and J.M. Tendler and R.J. Eickemeyer and J.B. Joyner. POWER5 System Microarchitecture. IBM Journal of Research and Development, 49(4/5):505-521, 2005. (Pubitemid 41398400)
3. R. Bitirgen, E. Ipek, and J. Martinez. Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach. In Proc. of the 41th IEEE/ACM Intl. Symp. on Microarchitecture (MICRO), 2008.
4. E. Ebrahimi, O. Mutlu, C. Lee, and Y. Patt. Coordinated Control of Multiple Prefetchers in Multi-Core Systems. In Proc. of the 42th IEEE/ACM Intl. Symp. on Microarchitecture (MICRO), 2009.
5. E. Ebrahimi, O. Mutlu, and Y. Patt. Techniques for Bandwidth-efficient Prefetching of Linked Data Structures in Hybrid Prefetching Systems. In 15th Intl. Symp. on High Performance Computer Architecture(HPCA), 2009.
6. P. Emma. Understanding Some Simple Processor-Performance Limits. IBM Journal of Research and Development, 41(3), 1997.
7. F. Liu and Y. Solihin. Understanding the Behavior and Implications of Context Switch Misses. ACM Trans. on Architecture and Code Optimization (TACO), 7(4):21:1-28, 2010.
8. G. Hinton and D. Sager and M. Upton and D. Boggs and D. Carmean and A. Kyker and P. Roussel. The Microarchitecture of the Pentium 4 Processor. Intel Technology Journal, (Q1), 2001.
9. H.Q. Le and W.J. Starke and J.S. Fields and F.O. Connell and D.Q. Nguyen and B.J. Ronchetti and W.M Sauer and E.M. Schwarz and M.T. Waden. IBM Power6 Microarchitecture. IBM Journal of Research and Development, 51:639-662, 2007.
10. I.B. Vapnyarskii. Numerical Methods of Solving Problems of the Mathematical Theory of Standardization. USSR Computational Mathematics and Mathematical Physics, 18(2):484-487, 1978.
11. IBM. IBM Power4 System Architecture White Paper, 2002.
12. E. Ipek, O. Mutlu, J. Martinez, and R. Caruana. Self-Optimizing Memory Controller: A Reinforcement Learning Approach. In Proc.of the 35th Intl. Symp. on Computer Architecture (ISCA), 2008.
13. ITRS. International Technology Roadmap for Semiconductors: 2005 Edition, Assembly and packaging. In http://www.itrs.net/Links/2005ITRS/AP2005.pdf, 2005.
14. X. Jiang, N. Madan, L. Zhao, M. Upton, R. Iyer, S. Makineni, D. Newell, Y. Solihin, and R. Balasubramonian. CHOP: Adaptive Filter-Based DRAM Caching for CMP Server Platforms. In Proc. of the 16th Intl. Symp. on High Performance Computer Architecture (HPCA), 2010.
15. X. Jiang, N. Madan, L. Zhao, M. Upton, R. Iyer, S. Makineni, D. Newell, Y. Solihin, and R. Balasubramonian. CHOP: Integrating DRAM Caches for CMP Server Platforms. IEEE Micro Top Picks, 31(1):99-108, 2011.
16. X. Jiang, A. Mishra, L. Zhao, R. Iyer, Z. Fang, S. Srinivasan, S. Makineni, P. Brett, and C. Das. ACCESS: Smart Scheduling for Asymmetric Cache CMPs. In Proc. of the 17th Intl. Symp. on High Performance Computer Architecture (HPCA), 2011.
17. X. Jiang and Y. Solihin. Architectural Framework for Supporting Operating System Survivability. In Proc. of the 17th Intl. Symp. on High Performance Computer Architecture (HPCA), 2011.
18. X. Jiang, Y. Solihin, L. Zhao, and R. Iyer. Architecture Support for Improving Bulk Memory Copying and Initialization Performance. In Proc. of the 18th Intl. Conf. on Parallel Architecture and Compilation Techniques (PACT), 2009.
19. N. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. In Proc. of the 17th Intl. Symp. on Computer Architecture, 1990.
20. C. Lee, O. Mutlu, V. Narasiman, and Y. Patt. Prefetch-Aware DRAM Controller. In Proc. of the 41th IEEE/ACM Intl. Symp. on Microarchitecture (MICRO), 2008.
21. J. Little. A Proof of Queueing Formula L =λW. Operations Research, 9(383-387), 1961.
22. F. Liu, F. Guo, S. Kim, A. Eker, and Y. Solihin. Characterizing and Modeling the Behavior of Context Switch Misses. In Proc. of the 17th Intl. Conf. on Parallel Architecture and Compilation Techniques (PACT), 2008.
23. F. Liu, X. Jiang, and Y. Solihin. Understanding How Off-Chip Memory Bandwidth Partitioning in Chip Multiprocessors Affects System Performance. In 16th Intl. Symp. on High Performance Computer Architecture, 2010.
24. P. S. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner. Simics: A Full System Simulation Platform. IEEE Computer Society, 35(2):50-58, 2002.
25. O. Mutlu and T. Moscibroda. Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. In Proc. of the 40th IEEE/ACM Intl. Symp. on Microarchitecture (MICRO), 2007.
26. O. Mutlu and T. Moscibroda. Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems. In Proc.of the 35th Intl. Symp. on Computer Architecture (ISCA), 2008.
27. K. Nesbit, D. Aggarwal, J. Laudon, and J. Smith. Fair Queuing Memory System. In Proc. of the 39th IEEE/ACM Intl. Symp. on Microarchitecture (MICRO), 2006.
28. N. Rafique, W. Lim, and M. Thottethodi. Effective Management of DRAM Bandwidth in Multicore Processors. In Proc. of the 16th Intl. Conf. on Parallel Architectures and Compilation Techniques(PACT), 2007.
29. S. Rixner, W. Dally, U. Kapasi, P. Mattson, and J. Owens. Memory Access Scheduling. In Proc.of the 27th Intl. Symp. on Computer Architecture (ISCA), 2000.
30. B. Rogers, A. Krishna, G. Bell, X. Jiang, and Y. Solihin. Scaling the Bandwidth Wall: Challenges in and Avenues for CMP Scaling. In Proc. of the 36th Intl. Conf. on Computer Architecture (ISCA), 2009.
31. L. Spracklen, Y. Chou, and S. Spracklen. Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications. In 11th Intl. Symp. on High Performance Computer Architecture(HPCA), 2004.
32. S. Srikantaiah and M. Kandemir. SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs. In In Proc. of Intl. Conf. on High Performance Embedded Architectures and Compilers (HiPEAC), 2010.
33. S. Srinath, O. Mutlu, H. Kim, and Y. Patt. Feedback Directed Prefetching: Improving the Performance and Bandwidth-efficiency of Hardware Prefetchers. In 13th Intl. Symp. on High Performance Computer Architecture(HPCA), 2007.
34. Standard Performance Evaluation Corporation. Spec cpu2006 benchmarks. http://www.spec.org 2006.
35. X. Zhuang and H.-H. Lee. Reducing Cache Pollution via Dynamic Data Prefetch Filtering. IEEE Trans. on Computers, 56(1):18-31, 2007.