Characterizing and modeling the behavior of context switch misses

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2008, Pages 99-101

  Liu, Fang ^a   Guo, Fei ^a   Solihin, Yan ^a   Kim, Seongbeom ^b   Eker, Abdulaziz ^c  

^a North Carolina State University   (United States)

^b VMWARE INC   (United States)

^c Scientific and Technological Research Council of Turkey   (Turkey)

Author keywords

Analytical model; Context switch misses; Prefetching; Stack distance profiling

Indexed keywords

ANALYTICAL MODEL; CACHE DESIGNS; CACHE MISS; CACHE PARAMETERS; CACHE REPLACEMENT POLICIES; CACHE SIZES; CONTEXT SWITCH MISSES; CONTEXT SWITCHING; MATHEMATICAL RELATIONSHIPS; MODERN COMPUTER SYSTEMS; MULTIPLE THREADS; PERTURBATION EFFECTS; PREFETCHING; SIMULATION STUDIES; STACK DISTANCE PROFILING; WORKING SETS;

APPLICATIONS; COMPUTER SIMULATION; DECODING; PARALLEL ARCHITECTURES;

DATA STORAGE EQUIPMENT;

EID: 63549130253     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1454115.1454130     Document Type: Conference Paper

References (21)

1. A. Agarwal and J. Hennessy and M. Horowitz. An Analytical Cache Model. ACM Trans. on Computer Systems, 7(2):184-215, 1989.
2. A. Agarwal, J. Hennessy, and M. Horowitz. Cache Performance of Operating System and Multiprogramming Workloads. ACM Trans. on Computer Systems, 6(4):393-431, 1988.
3. C. Cascaval and David A. Padua. Estimating Cache Misses and Locality Using Stack Distances. In Proc. of 17th Intl. Conf. on Supercomputing, pages 150-159, 2003.
4. C. Cascaval, L. DeRose, D. A. Padua, and D. Reed. Compile-Time Based Performance Prediction. In Proc. of the 12th Intl. Workshop on Languages and Compilers for Parallel Computing, pages 365-379, 1999.
5. F. M. David, J. Carlyle, and R. H. Campbell. Context Switch Overheads for Linux on ARM Platforms. In Proc. of the 2007 Workshop on Experimental Computer Science, 2007.
6. R. Fromm and N. Treuhaft. Revisiting the Cache Interference Costs of Context Switches. http://citeseer.ist.psu.edu/252861.html, 1996.
7. G. Edward Suh and S. Devadas and L. Rudolph. Analytical Cache Models with Applications to Cache Partitioning. In Proc. of Intl. Conf. on Supercomputing, pages 1-12, 2001.
8. G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker and P. Roussel. The Microarchitecture of the Pentium 4 Processor. Intel Technology Journal, (1Q), 2001.
9. F. Guo and Y. Solihin. An Analytical Model for Cache Replacement Policy Performance. In Proc. of the ACM SIGMETRICS/Performance 2006 Joint Intl. Conf. on Measurement and Modeling of Computer System, pages 228-239, 2006.
10. IBM. IBM Power4 System Architecture White Paper, 2002.
11. N. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. In Proc. of the 17th Intl. Symp. on Computer Architecture, pages 364-373, 1990.
12. P. Koka and M. H. Lipasti. Opportunities for Cache Friendly Process Scheduling. In Workshop on Interaction Between Operating Systems and Computer Architecture, 2005.
13. H. Kwak, B. Lee, A. Hurson, S. Yoon, and W. Hahn. Effects of Multithreading on Cache Performance. IEEE Trans. on Computers, 48(2):176-184, 1999.
14. C. Li, C. Ding, and K. Shen. Quantifying The Cost of Context Switch. In Proc. of the 2007 Workshop on Experimental Computer Science, 2007.
15. P. S. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner. Simics: A Full System Simulation Platform. IEEE Computer Society, 35(2):50-58, 2002.
16. R. L. Mattson, J. Gecsei, D. Slutz, and I. Traiger. Evaluation Techniques for Storage Hierarchies. IBM Systems Journal, 9(2):78-117, 1970.
17. J. Mogul and A. Borg. The Effect of Context Switches on Cache Performance. In Proc. of the 4th Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, pages 75-84, 1991.
18. Standard Performance Evaluation Corporation. Spec cpu2006 benchmarks. http://www.spec.org, 2006.
19. G. E. Suh, S. Devadas, and L. Rudolph. A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning. In Proc. of Intl. Symp. on High Performance Computer Architecture, pages 117-126, 2002.
20. D. Thiebaut and H. S. Stone. Footprints in the Cache. ACM Trans. on Computer Systems, 5(4):305-329, 1987.
21. D. Tsafrir. The Context-Switching Overhead Inflicted by Handling Hardware Interrupts. In Proc. of the 2007 Workshop on Experimental Computer Science, 2007.