메뉴 건너뛰기




Volumn 46, Issue 6, 2011, Pages 1360-1370

A 10-bit, 40-MS/s, 1.21 mW pipelined SAR ADC using single-ended 1.5-bit/cycle conversion technique

Author keywords

Analog to digital converter (ADC); area efficient; pipelined SAR; single ended; successive approximation (SAR); switching op amp

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; AREA EFFICIENT; PIPELINED SAR; SINGLE-ENDED; SUCCESSIVE APPROXIMATIONS;

EID: 79957643227     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2126390     Document Type: Article
Times cited : (56)

References (21)
  • 2
    • 0036116461 scopus 로고    scopus 로고
    • A 1.2 V 10 b 20MSample/s non-binary successive approximation ADC in 0.13 μm CMOS
    • F. Kuttner, "A 1.2 V 10 b 20MSample/s non-binary successive approximation ADC in 0.13 μm CMOS," in IEEE ISSCC Dig. Tech Papers, 2002, pp. 176-177.
    • (2002) IEEE ISSCC Dig. Tech Papers , pp. 176-177
    • Kuttner, F.1
  • 3
    • 33845655208 scopus 로고    scopus 로고
    • A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS
    • DOI 10.1109/JSSC.2006.884231
    • S.W.Michael and R.W. Brodersen, "A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006. (Pubitemid 44955493)
    • (2006) IEEE Journal of Solid-State Circuits , vol.41 , Issue.12 , pp. 2669-2680
    • Chen, S.-W.M.1    Brodersen, R.W.2
  • 5
    • 77952201627 scopus 로고    scopus 로고
    • Pipeline of successive approximation converters with optimum power merit factor
    • J. Li and F. Malberti, "Pipeline of successive approximation converters with optimum power merit factor," in IEEE ICECS Dig. Tech. Papers, 2002, vol. 1, pp. 17-20.
    • (2002) IEEE ICECS Dig. Tech. Papers , vol.1 , pp. 17-20
    • Li, J.1    Malberti, F.2
  • 6
    • 41549143171 scopus 로고    scopus 로고
    • A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 μm CMOS
    • Apr.
    • S. M. Louwsma, A. J. M. Tuijl, M. Vertreqt, and B. Nauta, "A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 μm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 778-786, Apr. 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.4 , pp. 778-786
    • Louwsma, S.M.1    Tuijl, A.J.M.2    Vertreqt, M.3    Nauta, B.4
  • 7
    • 0018713960 scopus 로고
    • A high-speed 7 bit A/D converter
    • Dec.
    • R. J. Plassche and R. E. J. Grift, "A high-speed 7 bit A/D converter," IEEE J. Solid-State Circuits, vol. SC-14, no. 6, pp. 938-943,Dec. 1979.
    • (1979) IEEE J. Solid-State Circuits , vol.SC-14 , Issue.6 , pp. 938-943
    • Plassche, R.J.1    Grift, R.E.J.2
  • 9
    • 18544399632 scopus 로고    scopus 로고
    • 12-b digital-background-calibrated algorithmic ADC with -90-dB THD
    • DOI 10.1109/4.808906
    • O. E. Erdogan, P. J. Hurst, and S. H. Lewis, "A 12-b digital-background- calibrated algorithmic ADC with 90-dB THD," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1812-1820, Dec. 1999. (Pubitemid 32211363)
    • (1999) IEEE Journal of Solid-State Circuits , vol.34 , Issue.12 , pp. 1812-1820
    • Erdogan, O.E.1    Hurst, P.J.2    Lewis, S.H.3
  • 10
    • 0023564228 scopus 로고
    • C-2C ladder-based D/A converter for PCM codecs
    • Dec.
    • S. P. Singh, A. Prabhakar, and A. B. Bhattcharyya, "C-2C ladder-based D/A converter for PCM codecs," IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 1197-1200, Dec. 1987.
    • (1987) IEEE J. Solid-State Circuits , vol.SC-22 , Issue.6 , pp. 1197-1200
    • Singh, S.P.1    Prabhakar, A.2    Bhattcharyya, A.B.3
  • 12
    • 10444266682 scopus 로고
    • A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR
    • Dec.
    • Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2139-2151, Dec. 1990.
    • (1990) IEEE J. Solid-State Circuits , vol.39 , Issue.12 , pp. 2139-2151
    • Chiu, Y.1    Gray, P.R.2    Nikolic, B.3
  • 13
    • 0025568946 scopus 로고
    • A fast-settling CMOS op amp for SC circuits with 90-dB DC gain
    • DOI 10.1109/4.62165
    • K. Bult and G. J. G. M. Geelen, "A fast-settling CMOS op amp for SC circuits with 90-dB DC gain," IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1379-1384, Dec. 1990. (Pubitemid 21738088)
    • (1990) IEEE Journal of Solid-State Circuits , vol.25 , Issue.6 , pp. 1379-1384
    • Bult Klaas1    Geelen Govert, J.G.M.2
  • 14
    • 70349277453 scopus 로고    scopus 로고
    • A 12 b 50 MS/s fully differential zerocrossing- based ADC without CMFB
    • L. Brooks and H. S. Lee, "A 12 b 50 MS/s fully differential zerocrossing- based ADC without CMFB," in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 166-167.
    • (2009) IEEE ISSCC Dig. Tech. Papers , pp. 166-167
    • Brooks, L.1    Lee, H.S.2
  • 15
    • 63449097323 scopus 로고    scopus 로고
    • A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic source follower residue amplification
    • Apr.
    • J. Hu, N. Dolev, and B. Murmann, "A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic source follower residue amplification," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1057-1066, Apr. 2009.
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.4 , pp. 1057-1066
    • Hu, J.1    Dolev, N.2    Murmann, B.3
  • 16
    • 70349288305 scopus 로고    scopus 로고
    • A 50 MS/s 9.9 mW pipelined ADC with 58 dB SNDR in 0.18 μm CMOS using capacitive chargepumps
    • I. Ahmed, J. Mulder, and D. A. Johns, "A 50 MS/s 9.9 mW pipelined ADC with 58 dB SNDR in 0.18 μm CMOS using capacitive chargepumps," in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 164-165.
    • (2009) IEEE ISSCC Dig. Tech. Papers , pp. 164-165
    • Ahmed, I.1    Mulder, J.2    Johns, D.A.3
  • 19
    • 77957990877 scopus 로고    scopus 로고
    • A 12 b 50 MS/s 3.5 mW SAR assisted 2-stage pipeline ADC
    • C. C. Lee and M. P. Flynn, "A 12 b 50 MS/s 3.5 mW SAR assisted 2-stage pipeline ADC," in Symp. VLSI Circuits Dig. Tech. Papers, 2010, pp. 239-240.
    • (2010) Symp. VLSI Circuits Dig. Tech. Papers , pp. 239-240
    • Lee, C.C.1    Flynn, M.P.2
  • 20
    • 33947675327 scopus 로고    scopus 로고
    • 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC
    • DOI 10.1109/JSSC.2007.892169
    • B. P. Ginsburg and A. P. Chandrakasan, "500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739-747, Apr. 2007. (Pubitemid 46495390)
    • (2007) IEEE Journal of Solid-State Circuits , vol.42 , Issue.4 , pp. 739-747
    • Ginsburg, B.P.1    Chandrakasan, A.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.