Pipeline of successive approximation converters with optimum power merit factor

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 2002, Pages 17-20

  Li, Jinghua ^a   Maloberti, Franco ^b  

^a TEXAS A AND M UNIVERSITY   (United States)

^b The University of Texas at Dallas   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

12-BIT CONVERTERS; CMOS PROCESSS; CONVERTER ARCHITECTURE; FIGURE OF MERIT; INPUT FREQUENCY; LOW POWER; MERIT FACTOR; NYQUIST; POWER SUPPLY; SUCCESSIVE APPROXIMATIONS; TRANSISTOR LEVEL;

CMOS INTEGRATED CIRCUITS;

APPROXIMATION THEORY;

EID: 77952201627     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1045322     Document Type: Conference Paper

References (7)

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2. Markus Helfenstein, George S. Moschytz, "Circuits and Systems for Wireless Communications", Kluwer Academic Publishers, Boston, 2000.
3. Bang-Sup Song, Tompsett, M.F., Lakshmikumar, K.R., "A 12-bit 1-Msample/s Capacitor Error-averaging Pipelined A/D Converter". IEEE JSSC Vol 236, pp. 1324-1333, Dec. 1998.
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5. Abo, A.M., Gray, P.R. "A 1.5V, 10-bit, 14.3MS/S CMOS Pipeline Analog-to-digital Converter", IEEE Journal of Solid-State Circuits, Vol 345, pp. 599-606, May 1999.
6. Bult, K., Geelen, G. "A Fast-Settling CMOS op amp for SC Circuits with 90-dB DC Gain", IEEE Journal of Solid-State Circuits, Volume: 256, Dec. 1990, pp. 1379-1384.
7. Yong-In Park, S. Karthikeyan, Frank Tsay; Eduardo Bartolome, "A Low Power 10 bit, 80MS/s CMOS pipelined ADC at 1 SV Power Supply", I-580, ISCAS2001.