A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 380-381

  Liu, Wenbo ^a   Huang, Pingli ^a   Chiu, Yun ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITOR MISMATCH; CMOS TECHNOLOGY; CONVERSION PROCESS; DIGITAL BACKGROUND CALIBRATION; KT/C NOISE; LIMITING FACTORS; NANO-METER REGIMES; NON-IDEALITIES; PERFORMANCE-LIMITING FACTORS; PROCESS TECHNOLOGIES; RADIX 2; RAIL-TO-RAIL INPUT; REFERENCE VOLTAGES; SAMPLING SWITCHES; SAR ADC; SMALL CHIP AREA; SUCCESSIVE APPROXIMATION REGISTER; SWITCHING SPEED;

ANALOG TO DIGITAL CONVERSION; CAPACITANCE; CMOS INTEGRATED CIRCUITS;

ENERGY EFFICIENCY;

EID: 77952137366     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433830     Document Type: Conference Paper

References (4)

1. W. Liu et al., "A 600MS/s 30mW 0.13μm CMOS ADC Array Achieving Over 60dB SFDR with Adaptive Digital Equalization," ISSCC Dig. Tech. Papers, pp. 82-83, Feb. 2009.
2. J. McNeill, M. Coln, and B. Larivee, "A Split-ADC Architecture for Deterministic Digital Background Calibration of a 16b 1MS/s ADC," ISSCC Dig. Tech. Papers, pp. 276-278, Feb. 2005.
3. J. Li and U.-K. Moon, "Background Calibration Techniques for Multistage Pipelined ADC's with Digital Redundancy," IEEE TCAS-II, vol. 50, pp. 531-538, Sep. 2003.
4. B. Goll and H. Zimmermann, "A 0.12μm CMOS Comparator Requiring 0.5V at 600MHz and 1.5V at 6GHz," ISSCC Dig. Tech. Papers, pp. 316-317, Feb. 2007.