A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18μm CMOS using capacitive charge-pumps

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages

  Ahmed, Imran ^a   Mulder, Jan ^b   Johns, David A ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b Broadcom   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349288305     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977359     Document Type: Conference Paper

References (3)

1. B. Murmann and B.E. Boser, "A 12 b 75 MS/s Pipelined ADC Using Open-Loop Residue Amplification," ISSCC Dig. Tech. Papers, pp. 328-329, Feb. 2003
2. T. Sepke et al., "Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies," ISSCC Dig. Tech. Papers, pp. 812-813, Feb. 2006
3. J. Hu, N. Dolev, and B. Murmann, "A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Residue Amplification," IEEE Symp. VLSI Circuits, pp. 216-217, June 2008.