A 12b 50MS/s 3.5mW SAR assisted 2-stage pipeline ADC

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 239-240

  Lee, Chun C ^a,b   Flynn, Michael P ^a  

^a The Department of Civil and Environmental Engineering   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

B STAGES; CLOSED-LOOP BANDWIDTH; LOW POWER; NYQUIST; OUTPUT SWING; PIPELINE ADCS; SAR ADC;

VLSI CIRCUITS;

EID: 77957990877     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560243     Document Type: Conference Paper

References (5)

1. J. Craninckx and G. Van der Plas, "A 65fJ/conv.-step 0-to-50Ms/s 0-to-0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS", ISSCC Dig. Tech. Papers, pp. 246-247, Feb. 2007.
2. A. Panigada and I. Galton, "A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction", ISSCC Dig. Tech. Papers, pp. 162-163, Feb. 2009.
3. W. H. Yang et al., "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input," IEEE Journal of Solid-State Circuits, vol. 36, pp. 1931-1936, Dec. 2001.
4. I. Mehr and L. Singer, "A 55-mW 10-bit 40-Msample/s Nyquist-rate CMOS ADC," IEEE Journal of Solid-State Circuits, vol. 35, pp. 318-325, Mar. 2000.
5. S. H. Lewis, "Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications," IEEE Trans. Circuits Syst. II, vol. 39, pp. 516-523, Aug. 1992.