메뉴 건너뛰기




Volumn , Issue , 2011, Pages 216-226

Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODEL; AVERAGE PREDICTION ERROR; BLACK BOX APPROACH; EMPIRICAL MODEL; EMPIRICAL MODELING; HARDWARE OPTIMIZATION; KEY FEATURE; MACHINE-LEARNING; MECHANISTIC MODELING; MECHANISTIC MODELS; MECHANISTIC-EMPIRICAL MODEL; MECHANISTIC-EMPIRICAL PERFORMANCE MODEL; OVERFITTING; PARAMETERIZED; PENTIUM 4; PERFORMANCE MODEL; PROCESSOR CORES; PROCESSOR PERFORMANCE; REGRESSION MODELING; STATISTICAL INFERENCE; TRAINING DATA; UNDERLYING SYSTEMS; UNKNOWN PARAMETERS;

EID: 79957465443     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2011.5762738     Document Type: Conference Paper
Times cited : (39)

References (24)
  • 1
    • 4644226058 scopus 로고    scopus 로고
    • Microarchitecture optimizations for exploiting memory-level parallelism
    • June
    • Y. Chou, B. Fahs, and S. Abraham. Microarchitecture optimizations for exploiting memory-level parallelism. In ISCA, pages 76-87, June 2004.
    • (2004) ISCA , pp. 76-87
    • Chou, Y.1    Fahs, B.2    Abraham, S.3
  • 2
    • 47349128966 scopus 로고    scopus 로고
    • Microarchitecture design space exploration using an architecture-centric approach
    • Dec.
    • C. Dubach, T. M. Jones, and M. F. P. O'Boyle. Microarchitecture design space exploration using an architecture-centric approach. In MICRO, pages 262-271, Dec. 2007.
    • (2007) MICRO , pp. 262-271
    • Dubach, C.1    Jones, T.M.2    O'Boyle, M.F.P.3
  • 3
    • 33846480613 scopus 로고    scopus 로고
    • A performance counter architecture for computing accurate CPI components
    • Oct.
    • S. Eyerman, L. Eeckhout, T. Karkhanis, and J. E. Smith. A performance counter architecture for computing accurate CPI components. In ASPLOS, pages 175-184, Oct. 2006.
    • (2006) ASPLOS , pp. 175-184
    • Eyerman, S.1    Eeckhout, L.2    Karkhanis, T.3    Smith, J.E.4
  • 5
    • 33750834457 scopus 로고    scopus 로고
    • Characterizing the branch misprediction penalty
    • Mar.
    • S. Eyerman, J. E. Smith, and L. Eeckhout. Characterizing the branch misprediction penalty. In ISPASS, pages 48-58, Mar. 2006.
    • (2006) ISPASS , pp. 48-58
    • Eyerman, S.1    Smith, J.E.2    Eeckhout, L.3
  • 6
    • 0036296817 scopus 로고    scopus 로고
    • The optimal pipeline depth for a microprocessor
    • May
    • A. Hartstein and T. R. Puzak. The optimal pipeline depth for a microprocessor. In ISCA, pages 7-13, May 2002.
    • (2002) ISCA , pp. 7-13
    • Hartstein, A.1    Puzak, T.R.2
  • 7
    • 33846506102 scopus 로고    scopus 로고
    • Efficiently exploring architectural design spaces via predictive modeling
    • Oct.
    • E. Ipek, S. A. McKee, B. R. de Supinski, M. Schulz, and R. Caruana. Efficiently exploring architectural design spaces via predictive modeling. In ASPLOS, pages 195-206, Oct. 2006.
    • (2006) ASPLOS , pp. 195-206
    • Ipek, E.1    McKee, S.A.2    De Supinski, B.R.3    Schulz, M.4    Caruana, R.5
  • 8
    • 33748863916 scopus 로고    scopus 로고
    • Construction and use of linear regression models for processor performance analysis
    • Feb.
    • P. J. Joseph, K. Vaswani, and M. J. Thazhuthaveetil. Construction and use of linear regression models for processor performance analysis. In HPCA, pages 99-108, Feb. 2006.
    • (2006) HPCA , pp. 99-108
    • Joseph, P.J.1    Vaswani, K.2    Thazhuthaveetil, M.J.3
  • 9
    • 34548333834 scopus 로고    scopus 로고
    • A predictive performance model for superscalar processors
    • Dec.
    • P. J. Joseph, K. Vaswani, and M. J. Thazhuthaveetil. A predictive performance model for superscalar processors. In MICRO, pages 161-170, Dec. 2006.
    • (2006) MICRO , pp. 161-170
    • Joseph, P.J.1    Vaswani, K.2    Thazhuthaveetil, M.J.3
  • 10
    • 4644299010 scopus 로고    scopus 로고
    • A first-order superscalar processor model
    • June
    • T. Karkhanis and J. E. Smith. A first-order superscalar processor model. In ISCA, pages 338-349, June 2004.
    • (2004) ISCA , pp. 338-349
    • Karkhanis, T.1    Smith, J.E.2
  • 11
    • 35348870650 scopus 로고    scopus 로고
    • Automated design of application specific superscalar processors: An analytical approach
    • June
    • T. Karkhanis and J. E. Smith. Automated design of application specific superscalar processors: An analytical approach. In ISCA, pages 402-411, June 2007.
    • (2007) ISCA , pp. 402-411
    • Karkhanis, T.1    Smith, J.E.2
  • 12
    • 33846540871 scopus 로고    scopus 로고
    • Accurate and efficient regression modeling for microarchitectural performance and power prediction
    • Oct.
    • B. Lee and D. Brooks. Accurate and efficient regression modeling for microarchitectural performance and power prediction. In ASPLOS, pages 185-194, Oct. 2006.
    • (2006) ASPLOS , pp. 185-194
    • Lee, B.1    Brooks, D.2
  • 13
    • 77957818268 scopus 로고    scopus 로고
    • Efficiency trends and limits from comprehensive microarchitectural adaptivity
    • Mar.
    • B. Lee and D. Brooks. Efficiency trends and limits from comprehensive microarchitectural adaptivity. In ASPLOS, pages 36-47, Mar. 2008.
    • (2008) ASPLOS , pp. 36-47
    • Lee, B.1    Brooks, D.2
  • 14
    • 34748909426 scopus 로고    scopus 로고
    • Methods of inference and learning for performance modeling of parallel applications
    • Mar. 207
    • B. Lee, D. Brooks, B. R. de Supinski, M. Schulz, K. Singh, and S. A. McKee. Methods of inference and learning for performance modeling of parallel applications. In PPOPP, pages 249-258, Mar. 207.
    • PPOPP , pp. 249-258
    • Lee, B.1    Brooks, D.2    De Supinski, B.R.3    Schulz, M.4    Singh, K.5    McKee, S.A.6
  • 15
    • 66749185800 scopus 로고    scopus 로고
    • CPR: Composable performance regression for scalable multiprocessor models
    • Nov.
    • B. Lee, J. Collins, H. Wang, and D. Brooks. CPR: Composable performance regression for scalable multiprocessor models. In MICRO, pages 270-281, Nov. 2008.
    • (2008) MICRO , pp. 270-281
    • Lee, B.1    Collins, J.2    Wang, H.3    Brooks, D.4
  • 16
    • 0033365427 scopus 로고    scopus 로고
    • Exploring instruction-fetch bandwidth requirement in wide-issue superscalar processors
    • Oct.
    • P. Michaud, A. Seznec, and S. Jourdan. Exploring instruction-fetch bandwidth requirement in wide-issue superscalar processors. In PACT, pages 2-10, Oct. 1999.
    • (1999) PACT , pp. 2-10
    • Michaud, P.1    Seznec, A.2    Jourdan, S.3
  • 17
    • 0042290630 scopus 로고    scopus 로고
    • Empirical versus mechanistic modelling: Comparison of an artificial neural network to a mechanistically based model for quantitative structure pharmacokinetic relationships of a homologous series of barbiturates
    • Dec.
    • I. Nestorov, M. Rowland, S. T. Hadjitodorov, and I. Petrov. Empirical versus mechanistic modelling: Comparison of an artificial neural network to a mechanistically based model for quantitative structure pharmacokinetic relationships of a homologous series of barbiturates. The AAPS Journal, 1(4):5-13, Dec. 1999.
    • (1999) The AAPS Journal , vol.1 , Issue.4 , pp. 5-13
    • Nestorov, I.1    Rowland, M.2    Hadjitodorov, S.T.3    Petrov, I.4
  • 18
    • 52249094635 scopus 로고    scopus 로고
    • Characterization of SPEC CPU2006 and SPEC OMP2001: Regression models and their transferability
    • Apr.
    • E. Ould-Ahmed-Vall, K. A. Doshi, C. Yount, and J. Woodlee. Characterization of SPEC CPU2006 and SPEC OMP2001: Regression models and their transferability. In ISPASS, pages 170-190, Apr. 2008.
    • (2008) ISPASS , pp. 170-190
    • Ould-Ahmed-Vall, E.1    Doshi, K.A.2    Yount, C.3    Woodlee, J.4
  • 19
    • 36949001762 scopus 로고    scopus 로고
    • Using model trees for computer architecture performance analysis of software applications
    • Apr.
    • E. Ould-Ahmed-Vall, J. Woodlee, C. Yount, K. A. Doshi, and S. Abraham. Using model trees for computer architecture performance analysis of software applications. In ISPASS, pages 116-125, Apr. 2007.
    • (2007) ISPASS , pp. 116-125
    • Ould-Ahmed-Vall, E.1    Woodlee, J.2    Yount, C.3    Doshi, K.A.4    Abraham, S.5
  • 20
    • 33845874613 scopus 로고    scopus 로고
    • A case forMLP-aware cache replacement
    • June
    • M. K. Qureshi, D. N. Lynch, O. Mutlu, and Y. N. Patt. A case forMLP-aware cache replacement. In ISCA, pages 167-177, June 2006.
    • (2006) ISCA , pp. 167-177
    • Qureshi, M.K.1    Lynch, D.N.2    Mutlu, O.3    Patt, Y.N.4
  • 21
    • 0015490730 scopus 로고
    • The inhibition of potential parallelism by conditional jumps
    • Dec.
    • E. M. Riseman and C. C. Foster. The inhibition of potential parallelism by conditional jumps. IEEE Transactions on Computers, C-21(12):1405-1411, Dec. 1972.
    • (1972) IEEE Transactions on Computers , vol.C-21 , Issue.12 , pp. 1405-1411
    • Riseman, E.M.1    Foster, C.C.2
  • 23
    • 43049128224 scopus 로고    scopus 로고
    • An instruction throughput model of superscalar processors
    • Mar.
    • T. M. Taha and D. S.Wills. An instruction throughput model of superscalar processors. IEEE Transactions on Computers, 57(3):389-403, Mar. 2008.
    • (2008) IEEE Transactions on Computers , vol.57 , Issue.3 , pp. 389-403
    • Taha, T.M.1    Wills, D.S.2
  • 24
    • 34547681859 scopus 로고    scopus 로고
    • Microarchitecture sensitive empirical models for compiler optimizations
    • Mar.
    • K. Vaswani, M. J. Thazhuthaveetil, Y. N. Srikant, and P. J. Joseph. Microarchitecture sensitive empirical models for compiler optimizations. In CGO, pages 131-143, Mar. 2007.
    • (2007) CGO , pp. 131-143
    • Vaswani, K.1    Thazhuthaveetil, M.J.2    Srikant, Y.N.3    Joseph, P.J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.