A performance counter architecture for computing accurate CPI components

ACM SIGPLAN Notices

Volumn 41, Issue 11, 2006, Pages 175-184

  Eyerman, Stijn ^a,b   Eeckhout, Lieven ^a,b   Karkhanis, Tejas ^a,b   Smith, James E ^a,b  

^a GHENT UNIVERSITY   (Belgium)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

Hardware performance counter architecture; Superscalar processor performance modeling

Indexed keywords

COMPUTER SIMULATION; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; SOFTWARE ENGINEERING;

HARDWARE PERFORMANCE COUNTER ARCHITECTURE; SUPERSCALAR PROCESSOR PERFORMANCE MODELING;

COMPUTER ARCHITECTURE;

EID: 33846480613     PISSN: 15232867     EISSN: None     Source Type: Journal    
DOI: 10.1145/1168918.1168880     Document Type: Conference Paper

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