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Volumn , Issue , 2009, Pages 59-62

W-2W current steering DAC for programming phase change memory

Author keywords

Binary weighted; Digital to analog converter (DAC); DNL; INL; Mismatch; Phase change memory; W 2W current mirror

Indexed keywords

BINARY-WEIGHTED; DIGITAL-TO-ANALOG CONVERTER (DAC); DNL; INL; MISMATCH; W-2W CURRENT MIRROR;

EID: 67650168196     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WMED.2009.4816148     Document Type: Conference Paper
Times cited : (18)

References (9)
  • 1
    • 49549091783 scopus 로고    scopus 로고
    • A Multi-Level-Cell Bipolar- Selected Phas- Change Memory
    • Ferdinando Bedschi, et al., "A Multi-Level-Cell Bipolar- Selected Phas- Change Memory", International Solid-State Circuits Conference, pp. 428-42, 2008.
    • (2008) International Solid-State Circuits Conference , pp. 428-42
    • Bedschi, F.1
  • 3
    • 85008054314 scopus 로고    scopus 로고
    • A 90nm 1.8V 512Mb Diode Switched PRAM with 266 MB/s Read Throughput
    • January
    • Kwang-Jin Lee, et al., "A 90nm 1.8V 512Mb Diode Switched PRAM with 266 MB/s Read Throughput", IEEE Journal of Solid-State Circuits, vol 43, pp. 150-162, January 2008.
    • (2008) IEEE Journal of Solid-State Circuits , vol.43 , pp. 150-162
    • Lee, K.-J.1
  • 4
    • 35848958587 scopus 로고    scopus 로고
    • Staircase-down SET programming approach for phase-change memories
    • DOI 10.1016/j.mejo.2007.07.121, PII S0026269207002492
    • Ferdinando Bedschi, Chiara Boffino, Edoardo Bonizzoni, Claudio Resta, Guido Torelli, "Staricase-down SET programming apporach for phasechange memory" Microelectronics Journal, vol 38, pp. 1064-1069, 2007. (Pubitemid 350060950)
    • (2007) Microelectronics Journal , vol.38 , Issue.10-11 , pp. 1064-1069
    • Bedeschi, F.1    Boffino, C.2    Bonizzoni, E.3    Resta, C.4    Torelli, G.5
  • 5
    • 42149105894 scopus 로고    scopus 로고
    • Write Strategies for 2 and 4 -bit Multilevel Phase- Change Memory
    • December
    • T.Nirschl, et al., " Write Strategies for 2 and 4 -bit Multilevel Phase- Change Memory", IEEE International Electron Devices Meeting, pp. 461-464, December 2007.
    • (2007) IEEE International Electron Devices Meeting , pp. 461-464
    • Nirschl, T.1
  • 7
    • 0003476558 scopus 로고    scopus 로고
    • Layout and Simulation, 2nd ed., Wiley- IEEE
    • R. Jacob Baker, CMOS Circuit Design , Layout and Simulation, 2nd ed., Wiley- IEEE, 2008.
    • (2008) CMOS Circuit Design
    • Baker, R.J.1
  • 9
    • 0028369135 scopus 로고
    • Measurement of MOS Current Mismatch in the Weak Inversion Region
    • February
    • Francesco Forti and Michael E. Wright, " Measurement of MOS Current Mismatch in the Weak Inversion Region" , IEEE Journal of Solid-State Circuits, vol. 29, pp. 138-142, February 1994.
    • (1994) IEEE Journal of Solid-State Circuits , vol.29 , pp. 138-142
    • Forti, F.1    Wright, M.E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.