HSPICE macromodel of PCRAM for binary and multilevel storage

IEEE Transactions on Electron Devices

Volumn 53, Issue 1, 2006, Pages 56-61

  Wei, X Q ^b   Shi, L P ^b   Walia, Rajan ^a,c   Chong, T C ^b   Zhao, R ^b   Miao, X S ^b   Quek, B S ^c  

^a IEEE

^b DATA STORAGE INSTITUTE   (Singapore)

^c INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

HSPICE macroniodel; Integrated circuit (IC); Multilevel storage; Nonvolatile memory (NVM); Phase change random access memory (PCRAM)

Indexed keywords

COMPUTER PROGRAMMING; COMPUTER SIMULATION; CRYSTALLIZATION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; NONVOLATILE STORAGE; PHASE CHANGE MEMORY; SIMULATORS;

MACROMODELS; MULTILEVEL STORAGE; PHASE CHANGE RANDOM ACCESS MEMORY (PCRAM);

RANDOM ACCESS STORAGE;

EID: 33947679297     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.860645     Document Type: Article

References (21)

1. S. Tehrani, E. Chen, M. Durlam, M. DcHerrera, J. M. Slaughter, J. Shi, and G. Kerszykowski, "High density submicron magnetoresistive random access memory," J. Appl. Phys., vol. 85, pp. 5822-5827, 1999.
2. R. E. Jones Jr., "Ferroelectric nonvolatile memories for embedded applications," in Proc. IEEE Custom Integrated Circuits Conf., 1998, pp. 431-138.
3. J. Maimon, E. Spall, R. Quinn, and S. Schnur, "Chalcogenide - Based nonvolatile memory technology," in Proc. IEEE Aerospace Conf., vol. 5, 2001, pp. 2289-2294.
4. S. Tyson, G. Wicker, T. Lowrey, S. Hudgens, and K. Hunt, "Nonvolatile, high density, high performance, PC memory," in Proc. Aero Space Conf., vol. 5, 2000, pp. 385-390.
5. S. R. Ovshinsky and H. Fritzsche, "Amorphous semiconductors for switching memory and imaging application," IEEE Trans. Electron Devices, vol. ED-20, no. 2, pp. 91-105, Feb. 1973.
6. R. G. Neal and J. A. Aseltine, "The applications of amorphous materials to computer memories," IEEE Trans. Electron Devices, vol. ED-20, no. 2, pp. 195-205, Feb. 1973.
7. S. Lai and T. Lowrey, "OUM- A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications," in IEDM Tech. Dig., 2001, pp. 36.5.1-36.5.4.
8. A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, and R. Bez, "Electronic switching in PC memories," IEEE Trans. Electron Devices, vol. 51, no. 4, pp. 452-459, Apr. 2004.
9. D. Ielmini, A. L. Lacaita, A. Pirovano, F. Pellizzer, and R. Bez, "Analysis of phase distribution in PC nonvolatile memories," IEEE Electron Device Lett., vol. 25, no. 7, pp. 507-509, Jul. 2004.
10. A. Pirovano, A. L. Lacaita, F. Pellizzer, S. A. Kostylev, A. Benvenuti, and R. Bez, "Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials," IEEE Trans. Electron Devices, vol. 51, no. 5, pp. 714-719, May 2004.
11. R. A. Cobley and C. D. Wright, "Spice modeling of PCRAM devices," Inst. Electr. Eng. Proc.-Sci. Meas. Technol., vol. 150, no. 5, Sep. 2003.
12. X. Q. Wei, L. P. Shi, W. Rajan, R. Zhao, X. S. Miao, and T. C. Chong, "Universal HSPICE model for chalcogenide based phase change memory elements," in Proc. IEEE Nonvolatile Memory Technology Symp., vol. 15-17, Nov. 2004, pp. 88-91.
13. Ovshinsky, "Reversible electrical switching phenomena in disordered structures," Phys. Rev. Lett., vol. 21, no. 20, pp. 1450-1452, 1968.
14. Fundamentals of Amorphous Semiconductors, National Academy of Sciences-Na. Res. Council, Washington, DC, 1972.
15. 3 pseudobinary amorphous thin films for an optical disk memory," J. Appl. Phys., vol. 69, no. 5, pp. 2849-2856, 1991.
16. W. A. Johnson and K. F. Mehl, "Reaction kinetics in processes of nucleation and growth," Trans. Amer. Inst. Min. Metall. Eng., vol. 135, pp. 416-42, 1932.
17. Technical presentation of Ovonyx, "Ovonic unified memory" [Online]. Available: http://www.ovonyx.com/technology.pdf
18. G. Wicker, Ph.D. dissertation, Wayne State Univ., Detroit, MI, 1996.
19. J. A. Connelly and P. Choi, Macromodeling with SPICE. Englewood Cliffs, NJ: Prentice-Hall, 1991, ch. 3.
20. J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuit -A Design Perspective. Englewood Cliffs, NJ: Prentice-Hall, 2003.
21. T. Haraszti, CMOS Memory Circuits. Norwell, MA: Kluwer, 2000.