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Volumn 13, Issue 6, 2005, Pages 762-765

Simultaneous Vt selection and assignment for leakage optimization

Author keywords

Low power; Multiple threshold voltage; Variability

Indexed keywords

APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LINEAR PROGRAMMING; MOSFET DEVICES; OPTIMIZATION;

EID: 23744433702     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.844304     Document Type: Article
Times cited : (14)

References (8)
  • 1
    • 0023401686 scopus 로고
    • BSIM: Berkeley short-channel IGFET model for MOS transistors
    • Aug.
    • B. J. Sheu, D. L. Scharfetter, P. K. Ko, and M. C. Jeng, "BSIM: Berkeley short-channel IGFET model for MOS transistors," IEEE J. Solid-State Circuits, vol. SC-22, no. 4, pp. 558-566, Aug. 1987.
    • (1987) IEEE J. Solid-state Circuits , vol.SC-22 , Issue.4 , pp. 558-566
    • Sheu, B.J.1    Scharfetter, D.L.2    Ko, P.K.3    Jeng, M.C.4
  • 3
    • 0030697754 scopus 로고    scopus 로고
    • Transistor sizing issues and tools for multithresh-hold CMOS technology
    • Jun.
    • J. Kao, A. Chandrakasan, and D. Antoniadis, "Transistor sizing issues and tools for multithresh-hold CMOS technology," in Proc. Design Automation Conf., Jun. 1997, pp. 409-414.
    • (1997) Proc. Design Automation Conf. , pp. 409-414
    • Kao, J.1    Chandrakasan, A.2    Antoniadis, D.3
  • 4
    • 0036049095 scopus 로고    scopus 로고
    • Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
    • Jun.
    • M. Anis, S. Areibi, M. Mahmoud, and M. I. Elmasry, "Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique," in Proc. Design Automation Conf., Jun. 2002, pp. 480-485.
    • (2002) Proc. Design Automation Conf. , pp. 480-485
    • Anis, M.1    Areibi, S.2    Mahmoud, M.3    Elmasry, M.I.4
  • 7
    • 0030146154 scopus 로고    scopus 로고
    • Power dissipation analysis and optimization of deep submicron CMOS digital circuits
    • May
    • R. X Gu and M. I. Elmasry, "Power dissipation analysis and optimization of deep submicron CMOS digital circuits," IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 703-713, May 1996.
    • (1996) IEEE J. Solid-state Circuits , vol.31 , Issue.5 , pp. 703-713
    • Gu, R.X.1    Elmasry, M.I.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.