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Volumn , Issue , 2007, Pages 111-118

Gate sizing by Lagrangian relaxation revisited

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK SKEW OPTIMIZATION; COMPUTER-AIDED DESIGN; DELAY FUNCTIONS; DUAL PROBLEMS; ELMORE DELAY MODEL; GATE SIZING; INTERNATIONAL CONFERENCES; LA-GRANGIAN RELAXATION; OBJECTIVE FUNCTIONS;

EID: 50249166712     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397252     Document Type: Conference Paper
Times cited : (14)

References (15)
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  • 2
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  • 3
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    • Chuang, W.1    Sapatnekar, S.S.2    Hajj, I.N.3
  • 4
    • 0032685389 scopus 로고    scopus 로고
    • Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
    • July
    • C.-P. Chen, C. C. N. Chu, and D. F. Wong, "Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation," IEEE TCAD, vol. 18, no. 7, pp. 1014-1025, July 1999.
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  • 5
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    • May
    • V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi, "Fast and exact transistor sizing based on iterative relaxation," IEEE TCAD, vol. 21, no. 5, pp. 568-581, May 2002.
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  • 6
    • 0036911571 scopus 로고    scopus 로고
    • Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
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    • Tennakoon, H.1    Seche, C.2
  • 7
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  • 8
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  • 9
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  • 10
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  • 11
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  • 13
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.