Gate sizing for cell library-based designs

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 847-852

  Hu, Shiyan ^a   Ketkar, Mahesh ^b   Hu, Jiang ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Dynamic programming; Gate sizing

Indexed keywords

COUDERT APPROACH; DISCRETE GATE SIZING PROBLEM; GATE SIZING; LOCALITY SENSITIVE HASHING;

ALGORITHMS; DYNAMIC PROGRAMMING; MICROPROCESSOR CHIPS; PROBLEM SOLVING; SEMICONDUCTOR MATERIALS;

GATES (TRANSISTOR);

EID: 34547315715     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375282     Document Type: Conference Paper

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