A 530 Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 4, 2011, Pages 777-788

  Zhou, Dajiang ^a   Zhou, Jinjia ^a   He, Xun ^a   Zhu, Jiayi ^b   Kong, Ji ^b   Liu, Peilin ^b   Goto, Satoshi ^a  

^a WASEDA UNIVERSITY   (Japan)

^b SHANGHAI JIAO TONG UNIVERSITY   (China)

Author keywords

DRAM bandwidth; embedded compression; frame recompression; H.264 AVC; QFHD; ultra high definition; video decoder

Indexed keywords

DRAM BANDWIDTH; EMBEDDED COMPRESSION; FRAME RECOMPRESSION; H.264/AVC; QFHD; ULTRA HIGH DEFINITIONS; VIDEO DECODER;

BANDWIDTH; BANDWIDTH COMPRESSION; MOTION PICTURE EXPERTS GROUP STANDARDS; VLSI CIRCUITS;

DECODING;

EID: 79953168363     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2109550     Document Type: Article

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