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Volumn , Issue , 2009, Pages 2009-2012

Bandwidth-efficient cache-based motion compensation architecture with DRAM-friendly data access control

Author keywords

Cache; Cache based motion compensation; H.264 AVC; Motion compensation

Indexed keywords

ACCESS CONTROL SCHEMES; BANDWIDTH REDUCTIONS; BURST LENGTH; CACHE; CACHE-BASED MOTION COMPENSATION; CONVENTIONAL SCHEMES; DATA ACCESS CONTROL; DATA MAPPINGS; DATA REUSE; EQUIVALENT BANDWIDTH; H.264/AVC; H.264/AVC DECODERS; REFERENCE DATA;

EID: 70349214829     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.2009.4960007     Document Type: Conference Paper
Times cited : (21)

References (6)
  • 1
    • 70349219761 scopus 로고    scopus 로고
    • Bandwidth optimized motion compensation hardware design for H.264/AVC HDTV decoder
    • August
    • C.-Y. Tsai, T.-C. Chen, T-W. Chen, and L.-G. Chen, "Bandwidth optimized motion compensation hardware design for H.264/AVC HDTV decoder," ISCAS 2005, pp. 273-276, August 2005.
    • (2005) ISCAS 2005 , pp. 273-276
    • Tsai, C.-Y.1    Chen, T.-C.2    Chen, T.-W.3    Chen, L.-G.4
  • 2
    • 34548844763 scopus 로고    scopus 로고
    • Memory Cache Based Motion Compensation Architecture for HDTV H.264/AVC Decoder
    • May
    • Y. Li, Y. Qu, and Y. He, "Memory Cache Based Motion Compensation Architecture for HDTV H.264/AVC Decoder," ISCAS 2007, pp. 2906 - 2909, May 2007.
    • (2007) ISCAS 2007 , pp. 2906-2909
    • Li, Y.1    Qu, Y.2    He, Y.3
  • 3
    • 21644476517 scopus 로고    scopus 로고
    • High Performance Synchronous DRAMs Controller in H.264 HDTV Decoder
    • Oct
    • J. Zhu, L. Hou, W. Wu, R. Wang, C. Huang, J.-T. Li, "High Performance Synchronous DRAMs Controller in H.264 HDTV Decoder," ICSCIT 2004, vol. 3, pp. 1621 - 1624, Oct. 2004
    • (2004) ICSCIT 2004 , vol.3 , pp. 1621-1624
    • Zhu, J.1    Hou, L.2    Wu, W.3    Wang, R.4    Huang, C.5    Li, J.-T.6
  • 4
    • 51749123956 scopus 로고    scopus 로고
    • An SDRAM controller optimized for high definition video coding application
    • May
    • J. Zhu, P. Liu, D. Zhou, "An SDRAM controller optimized for high definition video coding application", ISCAS 2008, pp. 3518 - 3521, May 2008
    • (2008) ISCAS 2008 , pp. 3518-3521
    • Zhu, J.1    Liu, P.2    Zhou, D.3
  • 5
    • 70349219541 scopus 로고    scopus 로고
    • Micron SDRAM MT48LC4M32B2 datasheet
    • Micron SDRAM MT48LC4M32B2 datasheet, www.micron.com
  • 6
    • 34548835459 scopus 로고    scopus 로고
    • A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications
    • Feb
    • C.-D. Chien, et al., "A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications," ISSCC 2007, pp. 282 - 603, Feb., 2007.
    • (2007) ISSCC 2007 , pp. 282-603
    • Chien, C.-D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.