Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 1069-1072

  Xianmin, Chen ^a   Peilin, Liu ^a   Jiayi, Zhu ^a   Dajiang, Zhou ^b   Goto, Satoshi ^b  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

^b WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE SCHEME; EXTERNAL MEMORY; H.264/AVC VIDEO; HARDWARE ARCHITECTURE; HARDWARE IMPLEMENTATIONS; HIGH DEFINITION; LATENCY PROBLEM; MACRO BLOCK; REALTIME PROCESSING;

ALGORITHMS; DECODING; HARDWARE; MOTION COMPENSATION; MOTION PICTURE EXPERTS GROUP STANDARDS; OPTICAL FILTERS;

CACHE MEMORY;

EID: 70350142436     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5117944     Document Type: Conference Paper

References (8)

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